On Sep 16, 2020, at 5:30, Rodney Brown via cctalk wrote: SYSWCS37 is for a Series 37 (and probably 37XE too which is the expanded-chassis model, the XE is mostly the SIMB expander). I think WCSLE1 is for a "Micro 3000 XE? (and probably also ?Micro 3000? which I think was same thing in a single chassis; faster than Series 37) and WCSLE2 is for the Micro GX/LX/RX (repackaging with CPU, RAM, PIC/GIC on one card) but may be wrong about that. I know I have seen documentation of this, and recently. Ah! HP Channels, Dec 1986, probably from the HP Computer Museum site. There is a Series 64 Reference/Training Manual PDF on bitsavers, that will shed some light on the architecture. It?s fancy: ECL, dual ALUs (driven by wider microcode word), central system bus bridged to up to three IMB-style I/O buses (room in the architecture for a fourth I think), memory cache. Writable control store too (this was not usual for the 3000 product line). In retrospect it looks like they threw everything they had at making a 3000 that would go kinda sorta fast and count have a lot of I/O devices (mostly GICs and ATPs) connected. The ATP was another Series 64 innovation, which was also made to fit on the Series 37 as the TIC and later Micro 3000s as the ATP/M; I think it had a dedicated 6809-like processor for each port?s data transmission needs and another 6809-like processor for every several ports? flow and modem control lines, and I think most of what it did was put something between the terminal and the 3000 that didn?t need to interrupt the 3000 until there was enough received data to actually complete a read request or initiate a break. <http://bitsavers.org/pdf/hp/3000/series60/30140-90005_Series_64_Reference_Training_Manual_Apr83.pdf> I am thinking the ?Series 68? upgrade was new front panel plastic and a tape with a new microcode file that implemented changes enabling system table expansions for MPE V/E. ?Series 70? was similar (some frequently used MPE routines were implemented as microcode) but also included hardware changes (memory cache increased from 8K to 128K). Yes. Not very well documented but clearly from the same family, they all use the ?Synchronous IMB? or SIMB bus. One interesting note from one of the HPJ articles is that the console interface that runs at power-up (before microcode is loaded from disc/tape) is not a separate microprocessor like it is on series 64/68/70 (and I think 4x/5x), it is a microprogram from a 16-bit-wide ROM that drives only 16 of the microinstruction word bits. Microcoded in C! Note that as it simulates a Series III at present, the MPE is MPE V/R, which is really a roll-up of MPE IV for the Series II/III. MPE V/P had disc caching, MPE V/E had expanded system tables and got updates for a while. MPE V/E T-MIT was the first release supporting ?Mighty Mouse? (Series 37). BUT, one of the special Series 37 instructions is one to tell the microcode whether MPE V/P or MPE V/E is being run! I?m sure development started before the release of MPE V/E and this came in handy for that. -Frank McConnell