On 8/23/2019 12:00 PM, Paul Koning via cctalk wrote: Why bother is my view. The problem is Three fold, a) The hardware people keep changing the internal details. b) A good compiler can see the the original program structure and optimize for that. c) The flat memory model as from FORTRAN or LISP where variables are random over the entire memory space scrambles your cache. With that said if you can make the optimization in defined some sort of MACRO format changing parameters would be simple and be effective unseen changes. Kind of the the early Compiler Compilers. I see RISC as emulation of the HARVARD memory model. A Harvard model would not take much change in programing other than not having a "SMALL" mode. Two 32 bit wide buses (data) (program) could be faster as external memory is more drum like with filling of caches rather than random memory than one large data path doing everything. I still favor the CLASSIC instruction set model. OP:AC:IX:OFFSET Core Memory made the machines slow with the memory restore cycle, Giving rise to CSIC like the PDP 11 to give a better use of that dead cycle. RISC is only fast because of the PAGE cycle of dynamic memory at the time. Too bad everything is all 8/16/32/64+ computing or say a 36 bit classic style cpu design could run quite effective at a few GHZ. Ben.