23 Jan
2006
23 Jan
'06
12:34 p.m.
From: "Roy J. Tellason" <rtellason at
blazenet.net>
On Friday 20 January 2006 02:57 pm, J.C. Wren wrote:
What's missing there is sound files, for when the thing is operating... :-)
Hi
I don't think he mentions the memory size.
Dwight
23 Jan
23 Jan
12:43 p.m.
I believe he did. It's a 32K static RAM. It's under "Features Of The
Sequencer Unit".
--jc
Dwight Elvey wrote:
From:
"Roy J. Tellason" <rtellason at blazenet.net>
On Friday 20 January 2006 02:57 pm, J.C. Wren wrote:
What's missing there is sound files, for when the thing is
operating... :-)
Hi
I don't think he mentions the memory size.
Dwight
4:45 p.m.
At 12:04 AM 1/24/06 +0000, you wrote:
Wow! Think of the current spike when those all energized! And people
thought TTL was bad!
(I think you
I believe he did. It's a 32K static RAM. It's under "Features Of The
Sequencer Unit".
That's cheating. He should have wired up 262144 relays :-) can get away with 1 relay per bit).
-tony
24 Jan
24 Jan
1:31 p.m.
I believe he did. It's a 32K static RAM.
It's under "Features Of The
Sequencer Unit".
That's cheating. He should have wired up 262144 relays :-) 
2:36 p.m.
On 1/24/2006 at 6:31 PM ard at p850ug1.demon.co.uk wrote:
But that could never happen. You would only write one
byte at a time, so
not more than 8 relays would switch at once.
Let's think about this...
Could you really make a memory cell with 1 relay per bit using standard
relays? Latching relays, perhaps, but regular "make on coil current/break
on no current" relays?
Then there's the issue of addressing. 32KB would probably entail a 7x8x8
structure.
I'd expect that being able to change the state of a bit might require an
extra relay or two per bit, given an XY-select sort of structure. How
about 4 relays per bit?
Of course, we could implement memory as a recirculating shift register,
which ought to be lots of fun to listen to...
Cheers,
Chuck
5:18 p.m.
On 1/24/2006 at 6:31 PM ard at p850ug1.demon.co.uk wrote:
Who said anything about 'standard' relays? I was certainly considering
multiple coil or latching realys.
With stnadard relays, you can make a latch with one relay (connect an NO
contact in series with the coil across the supply). You need to put a
break contact of some other relay in series with that so as to be able to
reset the latch
What I have not worked out is whether that break contact needs to be on a
separate relay for each bit, or wheter you can make some kind of tree
decoder structure that can only open the supply to one relay at a time. I
think the latter is possible (I am assuming the existance of
make-before-break relay contact sets so as not to have problems with
glitches).
Intuitively, if you can have a series tree structure of make contacts to
create a 1-of-n decoder, you can have a parallel structure of break
contacts too. It's not quite that easy, you need a separate set of
cotnacts on each decoder relay for each output. That means you need 256
pole relays to make a 8-bit to 256 output decoder. I suspect 8 pole
relays exist or could be made (4 and 6 pole certainly do), that means 32
of them to do the job of one 256 pole relay).
But that could never happen. You would only write
one byte at a time, so
not more than 8 relays would switch at once.
Let's think about this...
Could you really make a memory cell with 1 relay per bit using standard
relays? Latching relays, perhaps, but regular "make on coil current/break
on no current" relays?
Then there's the issue of addressing. 32KB would probably entail a 7x8x8
structure.
Se above.
I'd expect that being able to change the state of a bit might require an
extra relay or two per bit, given an XY-select sort of structure. How
about 4 relays per bit?
It's normally taken to be at least 4 transsitors per bit, but I think you
need fewer relays than that.
Of course, we could implement memory as a
recirculating shift register,
which ought to be lots of fun to listen to...
How about using uniselectors and having decimal (or octal) memory ?
-tony
8:14 p.m.
On 1/24/2006 at 10:18 PM ard at p850ug1.demon.co.uk wrote:
How about using uniselectors and having decimal (or
octal) memory ?
I suppose you might also include some Strowger switches for address
decoding...
Back when I was in high school (a very long time ago), a fellow built a
tic-tac-toe "computer" using stepping relays and other telephone gear,
including a rotary dial where one input one's move. (only 9 possibilities,
so that was convenient). The contraption would make its own move in
response. Readout was a 3x3 grid of 25W incandescent lamps.
It was fun to watch.
Cheers,
Chuck
25 Jan
25 Jan
3:55 p.m.
On Tuesday 24 January 2006 08:14 pm, Chuck Guzis wrote:
On 1/24/2006 at 10:18 PM ard at p850ug1.demon.co.uk
wrote:
I'd like to see a schematic of that one, if it exists...
--
Member of the toughest, meanest, deadliest, most unrelenting -- and
ablest -- form of life in this section of space, a critter that can
be killed but can't be tamed. --Robert A. Heinlein, "The Puppet Masters"
-
Information is more dangerous than cannon to a society ruled by lies. --James
M Dakin
How about using uniselectors and having decimal
(or octal) memory ?
I suppose you might also include some Strowger switches for address
decoding...
Back when I was in high school (a very long time ago), a fellow built a
tic-tac-toe "computer" using stepping relays and other telephone gear,
including a rotary dial where one input one's move. (only 9 possibilities,
so that was convenient). The contraption would make its own move in
response. Readout was a 3x3 grid of 25W incandescent lamps.
It was fun to watch.
3:52 p.m.
On Tuesday 24 January 2006 05:18 pm, Tony Duell wrote:
Or, if there's any resistance in series with that coil, couple a
negative-going pulse to it by way of a capacitor. This worked out real well
for me with a couple of SCRs one time, with a 100nF cap between the anodes.
The second one being turned on while the first one was already on would
definitely turn the first one _off_, in spite of them not being spec'd that
way. The loads in this case were #47 light bulbs.
--
Member of the toughest, meanest, deadliest, most unrelenting -- and
ablest -- form of life in this section of space, a critter that can
be killed but can't be tamed. --Robert A. Heinlein, "The Puppet Masters"
-
Information is more dangerous than cannon to a society ruled by lies. --James
M Dakin
Could you
really make a memory cell with 1 relay per bit using standard
relays? Latching relays, perhaps, but regular "make on coil
current/break on no current" relays?
Who said anything about 'standard' relays? I was certainly considering
multiple coil or latching realys.
With stnadard relays, you can make a latch with one relay (connect an NO
contact in series with the coil across the supply). You need to put a
break contact of some other relay in series with that so as to be able to
reset the latch
8:02 p.m.
With stnadard
relays, you can make a latch with one relay (connect an NO
contact in series with the coil across the supply). You need to put a
break contact of some other relay in series with that so as to be able to
reset the latch
Or, if there's any resistance in series with that coil, couple a 
24 Jan
24 Jan
7:24 p.m.
Chuck Guzis wrote:
Let's think about this...
Could you really make a memory cell with 1 relay per bit using standard
relays? Latching relays, perhaps, but regular "make on coil current/break
on no current" relays?
How about:
- use regular relays as you suggest, n+1 relays per word,
n relays are 'bit relays', the (n+1)'th relay is a 'clear relay'.
- a contact of each of the n bit relays is wired to latch the relay.
- a normally-closed contact on the clear relay of each word
supplies power to the latch contact for the n bit relays.
A write cycle for the word consists of the sequence:
1. pulse the clear relay for the word
(opens the latch circuit, bit relays are released)
2. 'gate' the data bus onto the coils of the bit relays,
the relays for bits="1" pull in and latch up.
... kind of like the write cycle for core memory where you have to
set all bits to the same state before changing some to the other state.
You get by with one relay per bit but have fixed overhead for each word.
A large word size may be advantageous to reduce the ratio
of fixed overhead per word.
I did a (small) design/experiment with some relays a while ago as a part of a project.
It was fun stuff, developing/wrapping-your-head-around some different design
principles regarding timing issues, economics (number of contacts available), etc.
The fellow's relay computer looks really neat (Ohh.. to have 400 relays).
It may be the only Von Neumann architecture relay computer to have been made
(or relay CPU to be more accurate, given the IC memory) (I'm presuming it's a
basic VN arch).
(Although I think there was a fellow by the name of Booth in England that
experimented with making an inexpensive machine, late 40s or early 50s, after
the stored program concept was developed. I don't remember the details, but it
may have used relays. I think it's mentioned in "Early British Computers"/
Simon Lavington/1980/Digital Press/DEC.)
8:01 p.m.
On 1/24/2006 at 4:24 PM Brent Hilpert wrote:
Chuck Guzis wrote:
What would the address selection logic look like? For 32K, it would be
7x8. For writing, I suppose you could use some steering diodes at each
relay and supply somewhat less than the pull-in current needed on the x and
y access, so that the addressed relay wouldn't pull in unless both x and y
signals were present.
I suppose readout could be accomplished with another set of contacts on the
select relays.
Doing a 32Kx8 would doubtless require some significant timing delays to
allow for mechanical settling of the relay contacts.
Mechanical systems can be very interesting.
Old pipe organs (before the advent of electronics and electricity) used a
mechanical memory to record the states of adjustable combinations. Usually
accomplished by flipping pawls one way or the other.
IIRC, the big Univac drum used on the 1107/1108 systems (FASTRAND II?) used
a mechanical system to position the heads. Essentially a system of levers
driven by solenoids(?) that decoded a binary signal into an absolute
position.
...and then there's the way a Teletype decodes incoming serial data that's
very clever.
Cheers,
Chuck
Let's think about this...
Could you really make a memory cell with 1 relay per bit using standard
relays? Latching relays, perhaps, but regular "make on coil
current/break
on no current" relays?
How about:
- use regular relays as you suggest, n+1 relays per word,
n relays are 'bit relays', the (n+1)'th relay is a 'clear relay'.
- a contact of each of the n bit relays is wired to latch the relay.
- a normally-closed contact on the clear relay of each word
supplies power to the latch contact for the n bit relays.
A write cycle for the word consists of the sequence:
1. pulse the clear relay for the word
(opens the latch circuit, bit relays are released)
2. 'gate' the data bus onto the coils of the bit relays,
the relays for bits="1" pull in and latch up.
25 Jan
25 Jan
7:45 p.m.
IIRC, the big Univac drum used on the 1107/1108
systems (FASTRAND II?) used
a mechanical system to position the heads. Essentially a system of levers
driven by solenoids(?) that decoded a binary signal into an absolute
position.
That sort of mechanism was used in some printing telegraph machines.
Decoding from n solenoids to 2^n positions of the typewheel.
I have a camera here with an analogue version of this. It combines the
positions of the shutter speed/film speed dial, the lens aperture ring,
and a dial set to the maximum aperture of the lens, and controls the
position of the reference pointer for the exposure meter.
Olivetti had a really odd mechanism in the TE300 teleprinter. It used a
number of cylinders, with offset holes, each cylinder fitting inside the
hole of the next larget one. A system of gears and cltuches rotated each
cylinder to 1 of 2 postions half a turn apart depending on the state of
each input bit. The position of a follower on the largest cylinder was
thus determined by all the bits that corolled the cylinders in that
mechanism.
Anmd then there's the well-knwon Creed combination head with the stack of
disks, each one rotated slghtly by a given input bit, and a set of
bellcrank levers that fit round the outside such that a different one
drops in place for each combination of positions of the input bits. And
the ends of these levers stop the rotation of the type wheel at the right
place.
...and then there's the way a Teletype decodes
incoming serial data that's
very clever.
Mechancial calculating machines are another set of interesting mechanisms
to look at ...
-tony
23 Jan
23 Jan
8:10 p.m.
On 1/24/2006 at 12:04 AM ard at p850ug1.demon.co.uk wrote:
Then there's the small matter of address decoding....
-Chuck
I believe he did. It's a 32K static RAM. It's under "Features Of The
Sequencer Unit".
That's cheating. He should have wired up 262144 relays :-) (I think you
can get away with 1 relay per bit). 
12:45 p.m.
At 09:34 AM 1/23/2006 -0800, you wrote:
Hi
I don't think he mentions the memory size.
Dwight
Aside from the various relay registers, he says:
"Main Memory (32K x 8bits, static RAM chip)"
And yes, audio would have been a nice addition to the video.
--tom
From: "Roy
J. Tellason" <rtellason at blazenet.net>
On Friday 20 January 2006 02:57 pm, J.C. Wren wrote:
What's missing there is sound files, for when the thing is
operating... :-)
12:50 p.m.
Dwight Elvey wrote:
Yes, he does -- it is a 32K x 8 SRAM.
Perhaps he is saving the memory system for another project -- perhaps a
dynamic ram made out of 128K leaky balloons and lots of tubing. :-)
From:
"Roy J. Tellason" <rtellason at blazenet.net>
On Friday 20 January 2006 02:57 pm, J.C. Wren wrote:
What's missing there is
sound files, for when the thing is operating... :-)
Hi
I don't think he mentions the memory size.
Dwight
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