18 Nov
2010
18 Nov
'10
8:41 p.m.
Sometimes the data sheets for an SARM (or whatever)
indicate the
row/column structure. Not that it matters, I've not come across an SRAM
that has, say, faster access time from a change in row address than a
change in column address
When I once asked why there were so many different PDP-11 memory diagnostics,
(beyond just unmapped vs mapped vs whatever processor diffs) I was
told that it was because each was structured to hit the row/column drivers
and induce known pattern-sensitive failure modes particular to the
core stack or chips in use.
Tim.
18 Nov
18 Nov
9:25 p.m.
Sometimes the data sheets for an SARM (or
whatever) indicate the=20
row/column structure. Not that it matters, I've not come across an SRAM=20
that has, say, faster access time from a change in row address than a=20
change in column address
When I once asked why there were so many different PDP-11 memory diagnostic=
s,
(beyond just unmapped vs mapped vs whatever processor diffs) I was
told that it was because each was structured to hit the row/column drivers
and induce known pattern-sensitive failure modes particular to the
core stack or chips in use. 
19 Nov
19 Nov
4:48 a.m.
On 18 Nov 2010 at 21:25, Tony Duell wrote:
But does it still make sense for semiconductor memory?
Are there
worst-case read/write sequences for SRAM or DRAM? I've certainly never
seen a data sheet which mentions them.
They exist, but are used by manufacturers, not customers to sniff out
problems in the chip design, such as unwanted crosstalk. Most of the
online cites I can come up with are behind subscription walls, but
look at US patent 7370250, for example.
Of course, that's not to say that even if the chip itself passes
worst-case tests, the memory array will. Problems with crosstalk,
decoupling, address-line drivers, etc. all make for an interesting
life.
--Chuck
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