Ack! How could I miss a discussion of the BI bus? I'd better pay a bit more attention when I'm glancing through the subject lines... I can vouch for this. The company I used to work for did a couple of VAXBI interface boards: a quad IEEE-488 board and an interface to a custom shared memory. DEC had to be convinced where product was complementary before it gave you the right to buy chips. There was a memory company that reverse engineered the BI bus, at least enough to build memory cards. Clearpoint, perhaps? I don't recall which. IIRC, they were bought by an I/O company (Emulex, maybe?) primarily to gain access to their reverse-engineered BI chip. There's also the fact that for the average bus transaction it really wasn't any faster than the UNIBUS. You had to _always_ do octaword transactions to outperform the UNIBUS (at least, the theoretical max of the UNIBUS; and by the time the VAXBI appeared, it was starting to be possible to get the theoretical max out of the UNIBUS. I once did a processor module that did the UNIBUS mapping during the settle(?) (the one that was after the deskew time) time; once that 75ns was up, the processor module knew that the adders had had enough time to map the address and didn't need to add any extra delay for the mapping. The processor module could support a J-11 running full bore while simultaneously outperforming the PDP-11/84 on DMA throughput. And it looked enough like a PDP-11/84 to run RSX-11 out of the box). I've still got a couple of copies of the VAXBI manual. Roger Ivie ivie(a)cc.usu.edu