On 10/23/2018 5:57 PM, Noel Chiappa via cctalk wrote:
PS:
Not the simplest machine to implement, mind - the
-8 is a lot
simpler.
As a rough measure of how much more complex, the -8/E and -11/20 are roughly
contemporaneous, and built out of the same technology (SSI TTL on larger
boards): the -8/E CPU is 5 quad boards, and the -11/20 CPU is 9 quad board
(equivalents - some are duals, etc).
Noel
I plan to design with MSI TTL but use 74LSXXX and a few CMOS 22v10's for
the hardware build.
The 22V10's are programed as simple roms.
The layout for a 18 bit data path, 1 20 alu card with 2 fill bits
or 2 12 bit cards with 3 fill bits per card.
If I use PAL logic I suspect I can put the whole cpu on large card, but
I need a simple instuction set.
For now it trial and error to see what fits best, but 16 bit CPU
extended to 18 bit data path looks to be most compact.
18..16.. 8.. .
[00][*OP*][AC][IX][index or #]
*op* OP code or jmp condition.
AC JMP,A,X,S
IX #,Z+index,X+index,S+index
Ben.