<800mA to switch! Ouch! No wonder the PSU was so bulky. Actually its 800ma per bit, the half select lines were some 400ma each plus sense inhibit signals. A large memory could easily be in the several tens of amps with all the surrounding logic. Typical power systems for code machines were very robust and heavy. <Truth. Trying to time right time to catch the bounce back and avoid <the read pulse that is there on the sense wire. Yeah, it's read in <serially fashion because that one wire is strung back and forth <through all cores just once. You have to fashion the circuit to <retore the orignal bits because the read process destroys the data. Sensing the read data is fairly easy as it will occur in a fixed point (all other things being constant) in time after the coincident select pulse. Coincident selection takes half the total current needed to switch the magnetic state of the core and divides it between two wires of the matrix where the two coincide is the selected core and the resulting magnetic field causes it to switch state. Writing is a matter of causing it to switch to the reverse state. ONE core in a larger array. Typical arrays are 16x16 or 64x64. A memory typically would contain many arrays organized as 4096 by 12 or 4096 by 16 or wider and possibly larger. One such machine the MIT/Lincoln TX2 had a main memory of 65536 38 bit words (2.5megabits). \ /---inhibit wire \|/ -----+----X SELECT wire /|\ / | \-----sense wire y --SELECTwire This is a single bit of a core plane, the + could be a doughnut of ferrite that can be magnetized in either direction depending on direction of current. The sense wire as that is a serpentine single wire that goes through each core. It's routing is such that for half the plane its sense is reverse to suppress induced noise from the select wires. Some planes use a forth wire threaded in the same way as an inhibit. Inhibit is so a one or zero representation can be forced. So we can select a core and read it's results and the selection process is in effect and erasure meaning we have to put back data. Reading is done by selecting a core using the X and Y select lines with thenough current to make the core magnetic filed to change if it was previosly different. This change or lack there of induces a current in the sense wire that we can detect. If there is no change in the magnetic field there will be a small pulse if there is a change in the field there will be a bigger pulse. Comparators are used to compare that pulse to a known reference and if big enough sends a pulse on to a latch (flipflop) to save that. Writing is like reading we select a core with the currents reversed to force the magnetization the other way, if we do not want to write we also force current through the inhibit wire so that it counters the magnetic field of the selection and inhibits the reversal. Before more detail is given it's sufficient to say that a core memory system is actually a goodly portion of the then current computers timing and cost. I have only glossed over the reson core works and the logic to do so is fairly involved as it requires sequential activities to occur precisely every time and at the correct time. Yes, core is destructive read out and the data read out must be stored written back. Most CPUs of the time would do a read/modify/write to take advantage of that. Living exampes of that include PDP-1 through PDP-11, TI990 and I believe NOVA. There is a whole class of logic that uses cores to propagate logic pulses and even perform logical operations on combinations of pulses. Cores have inherant memory from teh magnetization. There was a few computers built to exploit that and had few active devices(transistors or tubes). They are faster than relays but slower than tube or later transistor cicuits. Allison