8 Jan
2005
8 Jan
'05
2:51 a.m.
actually you can wire-or with diodes as long as you pay attention to the
"higher" low logic level. Naturally, the voltage is not TTL compatible, but I
have used that technique also. As for totem pole vs open collector, that is why I
mentioned reading the specs rather than getting more technical with output types. I
don't think anyone is going to whip out their TTL chips and start connecting them up
to see which one works and which one doesn't.
-----Original Message-----
From: Scott Stevens <chenmel(a)earthlink.net>
Sent: Jan 7, 2005 10:33 PM
To: "General Discussion: On-Topic and Off-Topic Posts"
<cctalk(a)classiccmp.org>
Subject: Re: RTL Logic
On Fri, 7 Jan 2005 12:59:57 -0800 (PST)
Tom Jennings <tomj(a)wps.com> wrote:
On Fri, 7 Jan 2005, Steve Thatcher wrote:
Wired-OR will work fine for open-collector output TTL. It will fail
miserably with totem-pole output parts. A 'battle of the transistors'
will ensue and one output or another will win.
dirt has been known to be found in most places in
the world...
doing a wired-or and wired-and depends on reading IC specifications
for specific chips. It is what design engineers do...
Sorry for being so obtuse! Phrase meant: "wire OR/etc was very
common in RTL".
I tried wired-OR once in TTL, didn't like the results :-)
8 Jan
8 Jan
11:15 p.m.
Wired-OR will work fine for open-collector output TTL.
Well, except you generally get wired-AND, because the open collectors
are generally NPN collectors with emitters to ground, not PNP
collectors with emitters to Vcc.
It will fail miserably with totem-pole output parts.
A 'battle of
the transistors' will ensue and one output or another will win.
Except that totem-pole outputs usually have just a transistor to
ground, but a transistor and resistor to Vcc. This means that the one
driving the signal low will win, and, provided not too many outputs are
wired together, it will sink the current without damage. (I've
actually built circuits that depended on this, though I've never liked
it and never considered it suitable for more than preliminary hackery.
I've also always never done it for anything where the conflict will
last more than nanoseconds, as when building an ~R/~S flip-flop out of
two cross-coupled inverters rather than the more usual NANDs or NORs.)
Of course, this depends on the details of the output pin circuitry and
hence does not really apply to things like CMOS TTL-alikes (unless they
go to the trouble to also simulate this aspect of TTL - I don't know
whether they do).
/~\ The ASCII der Mouse
\ / Ribbon Campaign
X Against HTML mouse(a)rodents.montreal.qc.ca
/ \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B
9 Jan
9 Jan
12:50 a.m.
der Mouse wrote:
That is twice you've tried to make this point. If a signal is viewed as
active low, then what is going on is logically wired-or. Imagine an
active low reset signal with two open collector drivers on it. If
either or both drivers pull down, then reset is activated. OR in this
case, not AND.
Wired-OR will
work fine for open-collector output TTL.
Well, except you generally get wired-AND, because the open collectors
are generally NPN collectors with emitters to ground, not PNP
collectors with emitters to Vcc.
4:26 a.m.
Wired-OR will work fine for open-collector output TTL.
Well, except you generally get wired-AND, because the open
collectors are generally NPN collectors with emitters to ground, not
PNP collectors with emitters to Vcc.
9:48 a.m.
der Mouse wrote:
That is twice you've tried to make this point. If a signal is viewed
as active low, then what is going on is logically wired-or.
Yes...but would you call (? of) a 7408 an OR gate if it happens to be
manipulating such signals? That's the sense in which I say it's
wired-AND: the resulting signal is what you'd get from feeding the same
logic levels (except with pullups, or non-OC outputs) into the gate
usually called an AND gate.
The schematic programs that I'm used to allow having different symbol
versions for situations like this, so the answer is yes: an OR gate gets
demorganized into what looks like an AND gate with bubbles on the inputs
and outputs. likewise, and AND get gets turned into an OR gate with
bubbles in inputs and outputs.
Wired-OR will
work fine for open-collector output TTL.
Well, except you generally get wired-AND, because the open
collectors are generally NPN collectors with emitters to ground, not
PNP collectors with emitters to Vcc.
7206
days inactive
7207
days old
4 comments
3 participants
participants (3)
-
frustum＠pacbell.net -
melamy＠earthlink.net -
mouse＠Rodents.Montreal.QC.CA