If the TI uses a DSUB-9 connector (I must be the only one here who doesn't have one), I wonder if the Tomy Tutor joysticks would work. I know TT joysticks are definitely not Atari compatible -- I nearly killed my C64 with one (remember that the joystick lines go right into the PLA, the glass jaw of the C64). -- ----------------------------- personal page: http://www.armory.com/~spectre/ -- Cameron Kaiser, Point Loma Nazarene University * ckaiser(a)stockholm.ptloma.edu -- I am the mother of all things, and all things must wear a sweater. ---------

Sure enough, there is. The pinouts for the Atari joystick -> TI-99 joystick port adapter are in the TI-99 FAQ at http://www.99er.net/tifaq.html --Mike

"Claude.W" wrote: Correct me if I'm wrong, but I've heard the 99/4A suffered something of an unfair rap for being slow due to the fact that its TI BASIC was dreadfully inefficient and sloppy, and that little or no blame for its slowness rested on the actual CPU or hardware. (Windoze users may spot a parallel here.) ;) The TMS 9900 CPU actually used a "window" in RAM as its register space, with an internal pointer register to locate its base address. This was actually a great idea at the time, because CPU cycles were long enough back then it made no difference whether you stored temporary values in internal registers or external RAM, as either could get you your data in the 1 cycle time available. (And interrupt latency can be really short if you can make a "fresh" register bank with one register load!) Most CPUs like the 8080 had barely enough registers (and special-purpose ones at that), so it was an advantage to use the wide-open RAM space for storage instead of doing a lot of register-shuttling XCHG-type stuff working with a tiny register set. It's one of the reasons that 6502 code density was so high, despite having obvious holes in the instruction set, because zero-page was effectively 256 byte registers and/or 128 16-bit pointers, indexing with them with two byte instructions. And why Z80 added indexing and extra register banks -- they were sorely needed. (/me - 8080 and 6502 programmer from way back. Talk to me about XCHG, PCHL, XTHL, and all kinds of neat tricks. It was fun but despite, not because of the CPU architecture.) Of course, modern RISC goes back to the load/store, many on-chip register model, but isn't it interesting that Berkley's SPARC uses register windows much like the TI does? -- Ross