William Donzelli wrote: of out This makes no sense. In every ECL family I have seen, when gates are assembled onto one die to make a logic function, the sum is always faster (often by a good amount) than if the same design was done using individual gates. Even if the individual gates are hand picked for speed, the complete logic function will be faster. And there is nothing to keep anyone from hand picking the complex logic functions for speed, as well. ---------------------------------- Seymour Cray did not like to use clocks. For example, his designs call for all the outputs of an adder to be perfectly aligned. He also did not like carry propagation, and wanted all the carrys out at the same time as the data. I've never seen LSI that could achieve this on 64 bit operands. Compare the speeds of some of his arithemetic units, especially the parallel multipliers, to LSI contemporary to his design. --------------------------------- There is also the speed gain of having more computing logic per board. For example in an individual gate design, the extra 2 inches of microstrip traces on the board, plus all the extras involved with getting the signal on and off each chip package, can add up to a significant part of a propagation delay of a gate. And, with more complex boards, the machine could get smaller, with a speed increase gained there as well, as the backplane (backnest?) would get smaller. ---------------------------------- But the switching time of even one gate is longer than the 2 inches of foil. His designs actually use the layout to deskew circuits. And he was big on cordwood packaging to eliminate the length of signal runs. Signals going off a module in all of his designs, are carefully timed and include the foil length and the board interconnects, be they wire or coaxial. All of what you say was true and carefully considered during design. Even where the modules were placed in a chassis was taken into account. I remember one chassis was completely re-laid out, to put the carry circuits in the center of the chassis because they had the longest propgation paths. ----------------------------------------------- This is certainly a valid reason, and for some of his later designs I can see where an ECL ALU (100181, for example) may have too many extra things. Ok, perhaps a bad example, as I do not think Cray designs use ALUs, or 100K, but it is what springs to mind. But, with something like an and-or-invert gate, or even a multiplexer or demultiplexor, the off the shelf designs are basically minimized. I know the Cray-1s ECL was something like MECL III or 100K, and certainly whoever the chip maker was could have supplied some basic logic functions beyond a gate or two. I think the extra effort to use them would have been minimal, with a great payoff. --------------------------------- When he left CDC, he looked at commercial logic families. And I believe he did do a design with MECL III. CDC proper moved on to MECL 10K for the Cyber 170s and MECL 100K for the STARs and ETA systems. Some CDC designs also used proprietory logic designs. But by then commercial logic suppliers were able to do a better job than in-house designers could and they were cheaper. Most of the in-house foundries were sold. CDC's was, and so was DEC's and Data General's. IBM moved on to be the power house foundry it is today. Makes you wonder who was right. Meanwhile, Seymour moved into more exotic logic trying to get more speed. I think he was working on a weird gallium-arsenide wafer scale design at the time of his death. At the time of the 6600, 7600 and Cray 1, there was no commercial family that could equal the speed of the Cray designs. Some came along (10K/100K) but they were real power hogs. Every gate had complimentary outputs. Every signal had to be terminated. The heat generated was so great that every IC had a heat sink under it, and the heat sink went to a freon cooled cold plate. I spent 4 year designing with MECL 10K. The experience was enough to convince to get out of design and go back to the field. It was a miserable family to work with. And I can assure you that there was skew on the outputs of any of the LSI blocks, but really bad on the 10181. Even with the special carry circuits, it took weeks of wire tuning to get the 96 bit floating point adder to work. We used to go back to the source (Seymour's design in the 7600) and marvel at it. 5 years after he designed it using transistors, we were still trying to equal his performance with MECL. ------------------------------- the I once heard that one of the big boxes in a computer room that hosted a Cray would have a fancy tag like "Disk Control" or something, but that was actually where the field engineer lived. --------------------------------- On my last field site, my office was called "Spares." -------------------------------------- Billy