On 01/31/2018 06:00 AM, Paul Koning via cctalk wrote: I believe that Honeywell went through a similar exercise at one point. An all-ECL redesign (details escape me) resulted in no appreciable improvement in performance. --Chuck

If you are comparing 74S/AS/F TTL to 10K ECL, you are making a unfair comparison. When the 74S and 10K were introduced in the very early 1970s, 10K ECL was not the fastest ECL available, MECL III was. MECL III was almost three times faster than 10K, but was expensive and difficult to use. It remained in front line use until the mid-1970s, simply because nothing could touch it. 10K became the popular ECL family because it was the easiest to use and would not break the bank. Additionally, when 74AS was introduced, 100K had already been established, with 10KH following shortly thereafter. 100K was very easy to deal with, as long as ALL the rules in the databooks were followed, but like MECL III, very expensive (a normal glue logic chip, like a 100101 triple OR/NOR was seven bucks in DIP, compared to thirty cents for something similar in TTL). Later still, 10E/100E was even faster, down to typical 400 pS gate delays - still something that TTL could not touch at the time. To top in off, 10G was a little faster that 10E/100E. Also, running 74S at full throttle often results in a real shitshow on the circuit board. It is far easier to run ECL at full speed potential. CMOS killed ECL, not TTL. -- Will

Then again, DEC Western Research Lab in the mid 1980s did an interesting project to do a full custom single ECL chip implementation of a MIPS (or Alpha?) CPU, intended to run at 1 GHz. The CAD system they built for this was quite interesting, as were bits of key technology like a heat pipe based chip cooling setup, possibly the first such device. It wasn't finished (the ECL fab shops kept going out of business faster than the CAD team could tweak the design rules in the tools) but some neat stuff came out of it, in internal reports only unfortunately. paul

On Wed, Jan 31, 2018 at 07:07:23PM -0800, Chuck Guzis via cctalk wrote: I really wish I still had one technical magazine that came out during the late 70s/early 80s. (I don't remember which one it was, anymore.) It was devoted to keeping you up with the latest chip/minicomputer technology. It contained a very serious editorial about "what are we going to use to replace CMOS" now that the > 10MHz chips were starting to be avialable. "Clearly" there was no way to push the technology past that: it was simply impossible due to heat dissipation -- the chips were going to burn up. It was an open-ended question; clearly neither ECL nor TTL were going to fit the bill. (Hey, at least the author got _that_ part correct.) Oh and while we're skewering early CMOS chips, they were grossly sensitive to static. The company I was working for during the summers was buying these $40 4-digit LED things with a CMOS driver and if you even looked at it wrong you could watch the chip swell up and bake underneath its protective plastic. This was not not very amusing to management. I'll bet I still have one in a box somewhere. mcl

Al Kossow wrote: Before I do anything rash, has anyone seriously tried to track down what happened to the F1 and/or its software?

Jonathan Katz wrote: Seems it was at Paramount at that time: "Probably the worst moment of my life with the Foonly came after we had managed to get it moved to Paramount Studios and were cranking through the film for a long sequence for Flight of the Navigator, a Disney film. http://dave.zfxinc.net/f1.html

Al Kossow wrote: This says the Superfoonly was designed. Doesn't say it was actually built. Triple-I funded the construction of the updated design, the F1. "The original superfoonly was designed at Stanford, on an ARPA contract, but Dave Poole, Phil Pettit, and Jack Holloway. There was also a fourth whose role (I think) was to build the CAD system which was used for the design. He later went to work for DEC. DEC took the foonly design and lobotomized it, which became the KL10. The other three came to Triple-I with a proposal to build an updated version of the original design (using ECL instead of TTL). http://dave.zfxinc.net/ddyer.html

Wayne S wrote: I don't think so. At least, I never heard that the F1 had such equipment.

On 1/31/18 12:25 PM, Al Kossow via cctalk wrote: Drawing http://www.scaruffi.com/svhistory/sil9.html Electronic Design Automation The S-1 project to build a supercomputer was started by the astrophysicist Lowell Wood at the Lawrence Livermore National Lab in 1975, first ran a program in 1978 and continued until 1988. Two Stanford students, Tom McWilliams and Curt Widdoes, were recruited to develop SCALD (Structured Computer-Aided Logic Design), an influential language to design computers, written in Pascal on DEC's PDP10 SCALD was based on the Stanford University Drawing System (SUDS) developed at Stanford's Artificial Intelligence Lab (SAIL) first by Phil Petit in 1969 on the PDP10 in assembly language) and later by Richard Helliwell. Petit moved to DEC and used SUDS to design the DEC KL-10 of 1973. Therefore SUDS became the first Computer Aided Design (CAD) system used to design an actual computer. Later Bechtolsheim used SUDS to design the SUN boards at SAIL. SCALD jumpstarted a whole new field, Electronic Design Automation (EDA) for electrical engineering and electronics. Tom McWilliams and Curt Widdoes started a company, initially called SCALD Corporation and later Valid Logic Systems, in 1981 in San Jose to sell SCALD on a proprietary UNIX workstation. At the same time, also in 1981 but in Mountain View, Aryeh Finegold and David Stamm used the public-domain source code for SCALD to found Daisy Systems, that also required a specialized workstation running its own Unix-like operating system. Several notable Silicon Valley founders (e.g. Vinod Khosla, Harvey Jones, Don Smith, Tony Zingale, Mike Schuh, George Haber, Dave Millman and Rick Carlson) started out at Daisy Systems. The third pioneer of EDA was Mentor Graphics, founded in 1981 in Oregon by Tektronix engineers (Tom Bruggere, Gerry Langeler and Dave Moffenbeier) and the only one that didn't require specialized hardware (it ran on regular Unix workstations). "released into the public domain in 1978." BFD. No one has a copy today.

On 1/31/18 6:25 PM, Rich Alderson via cctalk wrote: It would be good to get the actual history from the source. I was just parroting a summary, with SUDS as a tiny part. The observative will find Dick's name on some of the DEC SUDS-generated drawings, "S. Foonly" on others.

Lars Brinkhoff wrote: Confirmed by Dave Dyer: The original foonly design at Stanford was a paper design; I don't think there were actual schematics or board layouts. I believe it was proposed to be built using the best available TTL components. I think the F1 was essentially the same design, but obviously with full schematics and board layout, using faster ECL components.