20 Jun
2007
20 Jun
'07
4:16 a.m.
Subject: Re: T11 design WAS - Re: Inside old games machines,was: Re: Simulated CP/M-68K?
From: "e.stiebler" <emu at e-bbes.com>
Date: Tue, 19 Jun 2007 09:52:25 -0600
To: General Discussion: On-Topic and Off-Topic Posts <cctalk at
classiccmp.org>
Robert Borsuk wrote:
It's an easy cpu to interface and use. One of it's features is
that at reset the bus can be configured for 8 or 16 bit wide path,
for standard or varible microcycle and static memory or
Dram(with refresh).
I'd suspect the Dram support would be valuable in a game at a time
when large rams were dynamic.
Allison
I've been loosely following this thread and
never heard of a T11 from
DEC. So good'ole Google and Bitsavers saves the day, but it get's me
thinking. Has anybody done any design's with this processor? Why
wasn't this processor used instead of the 6100?
Rob
There is a guy who made his own SBC with a T-11, and even ported Forth
on it. I thought I knew his webpage, but it seems, I lost the bookmark.
But check google groups for "peter mccollum forth t11" and you will find
at least the discussions ... 
20 Jun
20 Jun
12:32 p.m.
On Wed, 20 Jun 2007, Allison wrote:
It's an easy cpu to interface and use. One of
it's features is
that at reset the bus can be configured for 8 or 16 bit wide path,
for standard or varible microcycle and static memory or
Dram(with refresh).
However, it's not without its obnoxious bits.
On the T-11, all writes are performed as read-modify-writes. This is
annoying when interfacing to chips such as the HDC9224 (the disk
controller used in the RQDX3). In that chip, you access many registers
through a single port address; another port indicates which of the
registers is being addressed. The internal address port increments on
either a read or a write. This means that a naive interface to the
HDC9224 from a T-11 A) increments the internal address register twice
and B) can't write register 0 because the internal address register is
incremented during the read.
IIRC, they handled this in the RQDX3 by placing the 9224 in two separate
address regions; one ignored reads, preventing them from getting to the
9224.
--
roger ivie
rivie at ridgenet.net
1:22 p.m.
New subject: T11 design WAS - Re: Inside old games machines, was: Re: Simulated CP/M-68K?
On 6/20/07, Roger Ivie <rivie at ridgenet.net> wrote:
On Wed, 20 Jun 2007, Allison wrote:
> It's an easy cpu to interface and use...
However, it's not without its obnoxious bits.
On the T-11, all writes are performed as read-modify-writes.
Hmm... was that because of the needs of core memory, or was it just to
simplify some aspect of its internal design?
RMW cycles are typically no problem with main memory, but I've seen
problems with them in a number of situations involving I/O, typically
involving "clever" peripherals that take a read of some register as a
trigger signal, but also with some 68000-family designs where you
weren't allowed to use instructions in your code which invoked RMW
cycles because they weren't interruptible (intentionally) and could
cause interrupt or instruction-restart problems.
At least with the 68000, RMW cycles were rarely done by real-world
code, and never accidentally.
With a from-scratch T-11 SBC, one could, I'd expect, select I/O
peripherals that wouldn't be subject to side-effects (like clearing
status bits on reads), but that's a lot harder when you have a mandate
to use a particular vendor's chip and the chip tries to be clever.
-ethan
9:09 p.m.
New subject: T11 design WAS - Re: Inside old games machines, was: Re: Simulated CP/M-68K?
On Wed, 20 Jun 2007, Ethan Dicks wrote:
On 6/20/07, Roger Ivie <rivie at ridgenet.net>
wrote:
I don't know anything about the internals, so I can't say. Although
AFAIK core was pretty much gone by the time the T-11 happened, it may have
been based on an earlier design that did interface to core.
--
roger ivie
rivie at ridgenet.net
On Wed, 20 Jun 2007, Allison wrote:
> It's an easy cpu to interface and use...
However, it's not without its obnoxious bits.
On the T-11, all writes are performed as read-modify-writes.
Hmm... was that because of the needs of core memory, or was it just to
simplify some aspect of its internal design? 
9:18 p.m.
New subject: T11 design WAS - Re: Inside old games machines, was: Re: Simulated CP/M-68K?
Roger Ivie wrote:
I don't know anything about the internals, so I
can't say. Although
AFAIK core was pretty much gone by the time the T-11 happened, it may
have been based on an earlier design that did interface to core.
I think a read
modify write may have made Dynamic ram interface simpler.
6394
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ajp166＠bellatlantic.net -
bfranchuk＠jetnet.ab.ca -
ethan.dicks＠gmail.com -
rivie＠ridgenet.net