replies to cctech Digest, Vol 53, Issue 52 - test-drb@ccmp.vtda.org

28 Jan 2008

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From: "UnR00ster" <unr00ster at gmail.com>
Subject: Re: 27256 in place of a 2764

...
 > Under what conditions can a 27256 be used in place
of a 2764?  I have a
> schematic that calls for the latter, of which I have none,
> but I have lots of the former. 
...
  See Ray Carlsen's site
 http://staff.washington.edu/rrcc/
 http://personalpages.tds.net/~rcarlsen/cbm/eprompla.txt
 adapters http://staff.washington.edu/rrcc/uwweb/EPROM/2x256.gif
 and http://staff.washington.edu/rrcc/uwweb/EPROM/2x128.gif
 This is all for Commodore stuff, but the idea of using a
 modified socket and 512K chip should work for you as well. 
Very clever!  I used to get EE trade rags and a regular advertisor
was a socket maker of "correct-a-dip": a daughter-board that you slip
under a chip to correct the pinout or add other parts,
kinda like the Slocket adapters for CPUs.
That's a nice way to do-it-yourself with easy to use, readily available parts
and no custom fabrication!

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From: "Chuck Guzis" <cclist at sydex.com>
Subject: Re:  Fast 8Kx2 ROM replacement
Message-ID: <479CF645.31339.23B64E5 at cclist.sydex.com>

...
  I don't have the message archives, but I don't
think that anyone
 mentioned the Cypress CY22016L NVSRAM using QuantumTrap technology.

 Pretty cool stuff; very fast SRAM backed by NV RAM;
 at power-up, the SRAM is loaded from the nonvolatile store;
 at power-down, it's written (optionally and probably not needed for this
application).

 The SRAM has access times of 25, 35 or 45 nsec. and unlimited writes.
 The NV RAM is guaranteed for 1,000,000 writes. 
Why not try for a free sample of the Freescale Magnetoresistive Random Access Memory
(MRAM):
it's fast and needs no power at all.
The largest seems to be P/N PR2A16AVYS35 4MBIT
     http://www.freescale.com/

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From: dwight elvey <dkelvey at hotmail.com>
Subject: RE: 8-bit micro MMU's
Message-ID: <BAY138-W18819E7D5B0F64A4281812A3340 at phx.gbl>

...
  One thing that is worth doing that I've seen done
on
 a Z8000 system is to map instruction memory into
 a different area of physical memory than the data memory.
 I don't recall but I think there is status information from
 the Z80 about what type of fetch or store is being done. 
I was pondering that long long ago: using the M1 line to differentiate
instruction fetch from data read/write.
Just one thing: unless it's an embedded system running only from ROM,
the loader needs to re-map data areas into program/executable space.

Before pipelines, pre-fetching and caches,
CPUs accessed RAM with a steady pace and pattern.
I can't be the only one to ponder using a Z80
where the M1 cycles (opcode fetch, refrech) went to ROM
and non M1 cycles went to RAM,
thus allowing other devices to "cycle steal" access to the RAM
without interfering with the CPU execution at all
(unlike DMA which halts the CPU,
or at least all the CPU's bus access).

-- Jeff Jonas