Al Kossow wrote: additional info from a posting by doug jones This has been done in many ways over the years. In 1960, a guy named Conway proposed the solution that Burroughs used for its commercial multiprocessors (they routinely sold 6 processor machines into the early 1980's). This involved a crossbar switch: | | CPU --+--+-- | | CPU --+--+-- | | M M Here, the cost of the interconnection goes up as the square of the number of CPU's. By 1973, they were able to build a 16 CPU system on this pattern at Carnegie-Mellon University. As long as each CPU used a different memory, they ran at full speed, but when two tried to access the same memory at the same time, they'd slow down. In the late 1970's, another scheme was invented, the snooping cache. Here, you hook things up like this: CPU CPU CPU ... CPU | | | | cache cache cache cache | | | | ---+-----+-----+-------+---+---+-----+-- | | | M M ... M Here, when a CPU accesses memory, it usually gets a local copy of the necessary value in its own cache. Only when the local cache hasn't got a copy of the value does the bus and the real memory get used. Of course, keeping all cached copies of the same meory location up to date when one CPU changes that location is a good trick, but the problem is solved by what are called snooping caches. Back in the 1980's, Sequent and Encore came out with machines supporting 16 to 64 processors built this way; DEC built the firefly workstation this way also -- using 4 microvaxen. There are other schemes that combine the virtues of the above two ideas, and these have allowed experimental systems with thousands of processors to be built. The recent announcement from Sun of a machine with 64 processors puts it at the high end of what I expect snooping caches to be able to do, but at the low end of the range successfully explored by the more complex interconnection systems. Multiprocessors aren't novel; they've been commercially available for 30 years! Doug Jones j... at cs.uiowa.edu