From: Ben Franchuk <bfranchuk(a)jetnet.ab.ca>
What I wanted was a 12/24 bit CPU. Other than the 6100
cpu ( over
priced? )
by DEC nobody has ever put a octal machine 24:12 or 18:9 or 36:18:9 on a
chip.
(Ignoring PDP-10 stuff) to my knowledge.
Right on very few if any! Most went to byte wide or multiples of byte
wide...
give a guess why? I've always felt that 24bvits was a good starting point
for a clean slate machine or a stretched PDP-8. By Stretched 8 I mean
just add 12 bits to the right and extend everything else the same amount,
gives you a 500k page address and a 16mb machine address. So what
if the instruction set is thin if done with modern FPGAs an easy 100ns
(12x faster) instruction cycle time would be fine.
I have yet to see a nice micro-code example. All the
micro-code
I have done ( on paper ) needed 32+ bits for a 2901 design.
Also about 2K of ROM. TTL controller. It got messy after you added
a MAR, In/out registers, and stuff like opcode decoding.
At 48 bits it gets better as then your not horozontal encoding.
Also if you use a prom to do the opcode to microaddress translation
it looks nicer and cuts a lot out. Also using the 2901 registers for
the PC and all saves a bit too. Still, as you noticed a lof of storage
bits for managing traffic are incurred. A combinational state machine
is simpler in some respects but far less flexible when it comes to
fixing a bent opcode.
Now that's
depressing. ;)
You tell me how I can make $$$ and I will not move to seattle.
I can't but, some things still taste bad. ;)
Allison