So, if one looks up the Cache Control Register in, say, the KDJ11-A (EK-KDJ1A-UG-002), one sees (in section 1.6.2.1) that there are _three_ ways to disable the cache: bits 2, 3 ('force miss'), and 9 ('bypass cache'). Looking at the DCJ11 manual (EK-DCJ11-UG-PRE) doesn't provide any additional insight. (The 9 bit one is slightly different than the other two, because it causes cache contents to be invalidated as the code runs, whereas the other two don't.) What is going on here, does anyone know? I'm _guessing_ that this is for compatability with the -11/70, where the cache is divided in two ('two-way set associative'), and either half can be disabled separately (using the 2 and 3 bits in its CCR). I suppose only someone who worked on the DCJ11 would know; but I have no idea how to track down such a person. Noel