4 Jul
2000
4 Jul
'00
9:06 a.m.
>2. The Catweasel uses a proprietary, largely
undocumented programming
>interface. My circuitry is entirely open, and I think it's pretty easy
>to program. (My first hack at acquiring data with the new buffer was
>dashed off in about half an hour under QBASIC.)
Thier doc's pretty much stink, or at least did when
I got mine!
It sounds like John Wilson has reverse-engineered at least *some* of
their programming interface, though last I heard there were parts of
the interface that were a mystery even to him :-).
>Would it be worth writing up my new floppy disk
data buffer so that
>others could improve on it? Would anyone be interested in unstuffed and/or
>stuffed PCB's? Should I give it a name? (The "Timweasel", anyone? I
>gotta think of a better name!)
Maybe/probably.
It looks like my circuit can be put on roughly a 3" x 4" PCB, meaning
that after paying for ExpressPCB overhead it'll be maybe $20 or so per
PCB in small quantities. The PCB would have a 24-pin header for interfacing
to a PC-clone parallel port (or whatever cabling you want to any other sort
of parallel type port on another hardware platform), and 34-pin and 50-pin
headers to hook to 3.5", 5.25", and 8" disk drives. I haven't priced
the chip costs, but they'll probably total around $25 or so from a hobby
place like Jameco or from a real distributor like Digi-Key.
Chip lineup in my current design:
1 62C1024 128K*8 SRAM.
1 74HCT373 for latching control signals from parallel port, 3 of
the outputs are used to drive the head load and step/direction
lines to the floppy drive.
8 MHz crystal clock.
1 74HCT74 for bi-phase clock generation and pulse synchronization from
the floppy read line
2 74HCT175's to make a seven-stage ring counter. Only 3 phase outputs are
used, one to latch and increment the counters, one to latch the
outputs of the shift register, and one to do the write enable.
1 74HCT164 for taking serial data from the 74HCT74 pulse synchronizer
and turning it into 7-bit wide parallel out.
(The 8th bit comes from the index line).
1 74HCT374 for latching the shift register data and tri-stating it onto
the memory buffer bus.
1 74HCT04 and 1 74HCT00 for gating and inverting as necessary
2 74HCT590's and 1 74HCT93 for making a 20-bit buffer address counter.
(17 bits are used in the current implementation, though
we obviously could just drop in a bigger SRAM and use
the extra address bits.)
I took some pains in my design to allow things to be sped up for more
oversampling at a later date. (I'd probably want to replace the 74HCT93
with a third 74HCT590 just to make all the address counters fully
synchronous, but I only had 2 HCT590's in my junk box when I built this
implementation). The timing from the ring counter and the
rest of the HCT logic ought to make sampling up to 40 MHz very straightforward
(I'd have to lengthen the write-enable from the ring counter at higher
clock speeds to cover a couple of clock phases).
It would be nice to stuff one in a Linux box, or will
it
work in an Alpha under VMS :^)
Anything with a bidirectional parallel port oughta work fine.
--
Tim Shoppa Email: shoppa(a)trailing-edge.com
Trailing Edge Technology WWW: http://www.trailing-edge.com/
7328 Bradley Blvd Voice: 301-767-5917
Bethesda, MD, USA 20817 Fax: 301-767-5927
4 Jul
4 Jul
9:33 a.m.
First, this is a really cool idea. I am glad someone has taken the time to
make it real.
At 02:06 PM 7/4/00 -0400, Tim wrote:
Chip lineup in my current design:
[bunch of parts]
8 MHz crystal clock.
1 62C1024 128K*8 SRAM.
1 Xilinx CPLD (XC9572 should more than handle
it)
The CPLD comes in a PLCC (44 pin) and thus is "hacker friendly" If you send
me a schematic I can generate a bit file for the PLD. Digikey sells these
for $5.53 in single quantities, if we can get by with fewer logic cells
then the cheaper one is $3.30 each in single quantities.
I took some pains in my design to allow things to be
sped up for more
oversampling at a later date.
The CPLD is supposed to run up to 100Mhz so you should have some head-room.
I could do a timing analysis at 16, 20, and 24Mhz and see if anything falls
out of spec.
Anything with a bidirectional parallel port oughta work
fine.
This is definitely the way to go, it has become a fairly "universal" interface.
Point me to the schematics and I'll see if it will fit in the smallest CPLD.
--Chuck
10:51 a.m.
8 MHz
crystal clock.
1 62C1024 128K*8 SRAM.
1 Xilinx CPLD (XC9572 should more than handle
it)
The CPLD comes in a PLCC (44 pin) and thus is "hacker friendly" If you send
me a schematic I can generate a bit file for the PLD. Digikey sells these
for $5.53 in single quantities, if we can get by with fewer logic cells
then the cheaper one is $3.30 each in single quantities. 
2:49 p.m.
The CPLD offers a number of advantages over FPGA's. They're not the same.
An FPGA uses a RAM lookup table in to define the function executed by a
logic cell. CPLD's use EPROM/EEPROM cells to store the logic configuration.
Most FPGA's require an external configuration prom of one sort or another,
which it boots on reset.
The FPGA has lots of logic available, though it's uncommon for more than
half of it to be useable. CPLD's have less logic, but it's all available
and often used up. Having several devices on the same footprint with
differing capacities is very useful, since you can then save money by using
a device that's "barely" enough without changing device packages.
Neither of these technologies offers enough drive to handle a FD cable,
however.
It's remarkable how little logic is needed to do a job like this one. Aside
advantage
from the buffer RAM, it's really quite simple. The
data rate is low enough
even at 32x that it easily allows writing a byte to the RAM
in or reading
from it in a single bit-time, and what looks to me as
the best candidate for
a cheap and ubiquitous part to use is a 1Mx4 DRAM. The
addresses can be
muxed in the CPLD and refresh (while it's idling) is easy to in hidden mode,
in which it uses an internal refresh counter. I don't know what 256Kx8
SRAMS cost these days (I could look ...) but if I already have 1Mx4 DRAMS,
it's easy to choose. The data port on the RAMs can be handled with a
single serial/parallel in, serial/parallel out shift register (like a 74195)
that allows you to operate on the data interface with the RAM each 4 bits by
either loading or reading the shift register.
I like this CPLD approach because anybody who wants to try their hand at
this can do so at no cost other than materials because the software is
available over the web, the programming cable schematic is available at
www.xilinx.com, and the software with which to program the things is also on
the web. The cable is even useable with other manufacturers' devices
because it is virtually standardized. My download cable is made such that I
can switch pins from one header to another so I don't have to have two
cables, one for XILINX and one for everyone else. It's not an expensive
arrangement, however. As I wrote previously, the software also provides a
really handy way to communicate schematics between folks working with the
same software.
I've not seen Tim's logic diagram for his sampler, but I do have one of my
own, and find that there's not enough logic involved to warrant use of a
CPLD in mine. It consists of a PAL, two counters, two shift registers and a
couple of 256Kx4 DRAMs. These components were chosen because I had them,
not because they lead to an elegant design. The entire sampling circuit
will easily fit into the small CPLD that's been suggested, including the
DRAM interface, and the interface to the PC's EPP port. If this thing is to
function as a rudimentary FDC, which would be VERY convenient, then it would
be easy enough to limit the current on the cable by keeping it short and
substituting larger resistor values for the 150-ohm numbers found on many
drives. That will solve the drive problem and shorter cables will not mind.
I'd encourage everybody to try it. These in-circuit programmables are
really neat! I like 'em LOTS better than FPGA's, though there are getting
to be a number of in-circuit programmable config proms as well.
Dick
----- Original Message -----
From: Eric J. Korpela <korpela(a)ellie.ssl.berkeley.edu>
To: <classiccmp(a)classiccmp.org>
Sent: Tuesday, July 04, 2000 1:51 PM
Subject: Re: Tim's own version of the Catweasel/Compaticard/whatever
> > 8 MHz crystal clock.
> > 1 62C1024 128K*8 SRAM.
> 1 Xilinx CPLD (XC9572 should more than handle it)
>
> The CPLD comes in a PLCC (44 pin) and thus is "hacker friendly" If you
send
> me a schematic I can generate a bit file for the
PLD. Digikey sells
these
for $5.53 in
single quantities, if we can get by with fewer logic cells
then the cheaper one is $3.30 each in single quantities.
I've actually been thinking about doing something like this. The of the FPGA is you could program it in situ. If you
know the controller
that
was really supposed to read the disk, you could
probably just emulate that
controller in the gate array. Of course, this is more complexity, but it
is optional complexity. The default configuration would be the sample
everything and sort it all out later version.
Eric
4:11 p.m.
The CPLD offers a number of advantages over
FPGA's. They're not the same.
An FPGA uses a RAM lookup table in to define the function executed by a
logic cell. CPLD's use EPROM/EEPROM cells to store the logic configuration.
Most FPGA's require an external configuration prom of one sort or another,
which it boots on reset.
Actually it's pretty easy to get an Xylinx FPGA to read a program from a
serial or parallel line, so all you need to do to reprogram is assert reset
and feed in the data correctly. But I can see your point on the CPLDs. I
generally go FPGA because I like to have lots of available logic for
flexibility's sake. Anyone have schematics for a large number of floppy
controllers? :)
Eric
4:34 p.m.
At 06:11 PM 7/4/00 -0700, someone wrote:
Not all FPGAs use RAM, infact it is one of the suggested advantages of
Xilinx FPGAs but it isn't a requirement. CPLDs generally have simpler
configuration blocks (or macrocells, or what ever the manufacturer wants to
call them)
The CPLD
offers a number of advantages over FPGA's. They're not the same.
An FPGA uses a RAM lookup table in to define the function executed by a
logic cell. CPLD's use EPROM/EEPROM cells to store the logic
configuration.
> Most FPGA's require an external configuration prom of one sort or another,
> which it boots on reset. Actually it's pretty easy to get an Xylinx FPGA to
read a program from a
serial or parallel line, so all you need to do to reprogram is assert reset
and feed in the data correctly.
This is true and the ultimate "catweasal" type board would have a nice fat
ram loaded FPGA connected to the interface logic and a high speed ram
buffer. Probably a programmable clock too. That way you could run anything
from an actual WD1793 type chip to an HP logic analyzer
just by downloading
a different setup.
--Chuck
6:05 p.m.
Please see embedded remarks below.
Dick
----- Original Message -----
From: Chuck McManis <cmcmanis(a)mcmanis.com>
To: <classiccmp(a)classiccmp.org>
Sent: Tuesday, July 04, 2000 7:34 PM
Subject: Re: Tim's own version of the Catweasel/Compaticard/whatever
to
downloading
At 06:11 PM 7/4/00 -0700, someone wrote:
> > The CPLD offers a number of advantages over FPGA's. They're not the
same.
> > An FPGA uses a RAM lookup table in to define
the function executed by
a
> > logic cell. CPLD's use EPROM/EEPROM
cells to store the logic
> configuration.
> > Most FPGA's require an external configuration prom of one sort or
another,
> which it
boots on reset.
Not all FPGAs use RAM, infact it is one of the suggested advantages of
Xilinx FPGAs but it isn't a requirement. CPLDs generally have simpler
configuration blocks (or macrocells, or what ever the manufacturer wants call them)
Well, the majority of them are RAM based because they get faster technology
out of the RAM-based setups and at lower cost. The real issue is
routability. With FPGA's, be they RAM LUT types or antifuse types, it's
pretty good if you get 60% utilization of the claimed available resources.
It's lower if you're redesigning a pin-locked design or one in which you
need to control timing very closely.
CPLD's OTOH, are almost always nearly 100% useable because of their
architecture. It's noticeably simpler, but that's to its credit.
Manufacturers of both make misleading claims, however. A typical Xilinx
part has a bunch of logic cells, normally consisting of pairs of 16-bit
lookup tables, easily concatenated into a 32-bit table, and, likewise,
easily useable as RAM in the later architectures. These things abound in
great numbers, but they're hard to interconnect. Making a design fit in the
larger arrays, at more than 50% utilization takes weeks, if not months, and
would have to be done for every configuration. I agree that you can program
them from a serial stream or a port as well as a prom of some sort. I just
find it easier to use the prom. A ram would work, too, but why bother if
you can do it from a parallel port?
I think you'll find the FPGA's a mite more expensive than the CPLD's. I
once looked for a small part on Avnet's site and found that only one of the
four available packages was under $1k each. COnsequently it's been a long
time since I used an FPGA from Xilinx. Their 5200 series is pretty
inexpensive, though, but still often over $50 per device. Moreover, DigiKey
doesn't carry the full line.
>Actually it's pretty easy to get an Xylinx
FPGA to read a program from a
>serial or parallel line, so all you need to do to reprogram is assert
reset
and feed in the
data correctly.
This is true and the ultimate "catweasal" type board would have a nice fat
ram loaded FPGA connected to the interface logic and a high speed ram
buffer. Probably a programmable clock too. That way you could run anything
from an actual WD1793 type chip to an HP logic analyzer just by a different setup.
Making all the functions come out in the same or at least similar FPGA's on
the same pins at the correct timing would be a lot of work. This function
is, by comparison, quite simple and, after all, the CPLD's are
in-situ-programmable. You could do the same trick, i.e. load them from your
parallel port. I submit, howver, that making a design work out in FPGA with
its limited routing resources, on a predetermined pinout would be a really
big job, i.e. assuming you want to put it the functions in a 179x and a 765,
plus the PLL and precomp logic, plus the drive selects, steering logic, I'd
say you're looking at a number of man-years unless you are able to get
in-house logic diagrams from Western Digital and NEC. Getting a
predermined pinout to work in a CPLD isn't always easy either, but a small
job like this one is a week's work.
--Chuck
10:51 a.m.
The only problem I'd point out is the the 9500 series CPLD's drive only 8 mA
per output and, unless you were planning to pair them up, i.e. use multiple
pins tied together to drive the FD cable, you might have problems.
I don't know about Tim's design, but I'd say the necessary logic to
interface via EPP will easily fit in the XC9572, and, in fact, one might
find an easy enough way to make an FDC fit in there as well.
The parts count with a SCENIX SX would be be lower, though, in that you need
one oscillator, e.g. 96 MHz, and one IC, the SX, which will comfortably
drive the cable. The SX-28 cost about $5.50 in onesies last time I acquired
some.
Yes, it's a really COOL idea, particularly with this particular CPLD family,
because the software with which to program them is FREE from their web site,
and you have the choice of doing it while on-line or downloading to your own
computer. Moreover, if you want to compare schematics with someone else,
you can do that if they have the same software, making schematics easy to
exchange.
Dick
----- Original Message -----
From: Chuck McManis <cmcmanis(a)mcmanis.com>
To: <classiccmp(a)classiccmp.org>
Sent: Tuesday, July 04, 2000 12:33 PM
Subject: Re: Tim's own version of the Catweasel/Compaticard/whatever
First, this is a really cool idea. I am glad someone
has taken the time to
make it real.
At 02:06 PM 7/4/00 -0400, Tim wrote:
send
Chip lineup in my current design:
[bunch of parts]
8 MHz crystal clock.
1 62C1024 128K*8 SRAM.
1 Xilinx CPLD (XC9572 should more than handle
it)
The CPLD comes in a PLCC (44 pin) and thus is "hacker friendly" If you
me a schematic I can generate a bit file for the PLD.
Digikey sells these
for $5.53 in single quantities, if we can get by with fewer logic cells
then the cheaper one is $3.30 each in single quantities.
head-room.
I took some pains in my design to allow things to
be sped up for more
oversampling at a later date.
The CPLD is supposed to run up to 100Mhz so you should have some I could do a timing analysis at 16, 20, and 24Mhz and
see if anything
falls
out of spec.
interface.
Anything with a bidirectional parallel port oughta
work fine.
This is definitely the way to go, it has become a fairly "universal"
Point me to the schematics and I'll see if it will fit in the smallest
CPLD.
--Chuck
8765
days inactive
8765
days old
7 comments
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CLASSICCMP＠trailing-edge.com -
cmcmanis＠mcmanis.com -
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richard＠idcomm.com