So, my guess was wrong there. I had _assumed_ that when doing a memory operation, the CPU started a cycle on both busses, to minimize the delay on the UNIBUS cycle if the MS11 on the FastBus didn't have that location. (I had previously checked, and there is an 'I have that location' signal which the MS11 sends back, making the concept of a cache possible.) Well, no. In the "KB11-A CPU Maintenance Manual" (DEC-11-HKBB-D), section 7.7.1 ("Bus Control Introduction"), it says: If the address applies to a Fastbus device, that device will respond in time to inhibit the UNIBUS MSYN signal (It turns out the KB11-A is very clever; it has to delay for a bit after asserting the address, etc, signals on the UNIBUS, for de-skew, before it can assert MSYN, and during that delay, in parallel, it checks to see if the MS11 has that location.) So my theory about what that double-card does (prevent an MSYN sent to main memory on a cache hit) is apparently wrong. Which leaves the question of what that card _does_ do... The cache _does_ need to have the A and B UNIBUS tied together, so that it can snoop UNIBUS memory cycles (which are on the A UNIBUS) via the B UNIBUS (which is what it has access to on the backplane), _but_ it doesn't need a special card, with i) active logic, and b) a cable back to the main board, to do that - a regular M9200 will do that. The cable back to the main card, and the logic on the two dual-width cards, mean it wants to interfere somehow in the connection between the A and B UNIBUS. But if not the MSYN thing, what else could it be? I have pondered that question, but I can't think of anything. It can't be doing anything with interrupts or DMA, I would think, so no grant interception. So what else could it be? Anyone have any ideas?

Noel