TI 990 architecture - test-drb@ccmp.vtda.org

3 Oct 2007

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Subject: Re: TI 990 architecture
   From: Cameron Kaiser <spectre at floodgap.com>
   Date: Tue, 02 Oct 2007 12:57:08 -0700 (PDT)
     To: cctalk at classiccmp.org

  If I remember right, the architecure of the ti
chip
 it used a pointer to ram as the internal registers. That would really
 bog down on byte wide bus. 
But then chips like the 9995 do very well on a 8-bit data bus. IMHO the
bigger problems with the 9900 implementation in the 99/4A were the external
scratch pad (made internal for the 9995) and the presence of GROMs, 
requiring their own interpretation step and murderously slow serial access.

Compare this to a system like the Tomy Tutor, which has a 9995 on an 8-bit
bus too, but is significantly faster than the 99/4A despite being clocked
slightly slower (10.7MHz oscillator instead of the 99/4A's 12MHz one). 
Actually My 99/4a has the 10.7 and the  actual CPU is clocked off the 
slower division of that. The clocks you note were used for the video timing.

However, the 9985 was a far nwer chip that the 9900 and was clocked 
internally faster.

Allison