It finally sunk into my brain what you are trying to do. Since I'm reading this on cctech with its day or two delay, this has probably been covered, but I'm sending it anyway. The purpose of the separate Din and Dout is that the IIfx SIMMs latched the write data so it could start the next read cycle before the write cycle was complete, saving a cycle or two at 40 MHz. I'm not sure that your idea will work for that. I think you'll need a tristate latch on the Din, maybe latched with WE# and enabled by WE# | CAS#. Dout could be tristated to ~(WE# | CAS#) | OE#. (if there is a separate OE#) There are a lot of caveats, though. I'm assuming that there is never a R/W cycle. I'm also assuming your DRAM outputs remain at high Z throughout a write only (aka "early write") cycle regardless of the state of OE#. If your DRAMS support this you can just ground the DRAM OE# and forget about it and just worry about when to tristate your buffers. Also watch out for systems that use WE# and OE# interchangably or mix them in funky ways. Your best bet is to study your DRAM datasheets carefully. It would be nice to have a IIfx timing diagram. I certainly don't have a logic analyzer fast enough for this task.... Eric