20 Oct
1999
20 Oct
'99
2:41 a.m.
-----Original Message-----
From: allisonp(a)world.std.com <allisonp(a)world.std.com>
To: Discussion re-collecting of classic computers
<classiccmp(a)u.washington.edu>
Date: Wednesday, October 20, 1999 9:49 AM
Subject: Re: OT: how big would it be?
I am going to impliment the instruction set serially... Hmm.. wonder where
I've seen that before?
I have run out of transistor/old computers to restore so I rfeally liked the
8/S and am going to do some fun stuff with a few hundred flip chips.
john
> BTW: I am building an Intel 4004 or possible an
8008 with flip chip
modules.
Will tell you
when I start it.
Those parts were in the 3000-6000 transistor bracket. I'd expect an 8008
in flip chips would be bigger than a straight-8 (that's larger than an
8S). Why? The 8008 is register rich compared to the PDP-8 series and
for every bit in a register thats a flip chip (8008 is about 45 bits of
registers alone and then there are the FFs in the state logic). This
thing is going to be HUGE. The 4004 would be less ambitious but there are
still a lot of FFs in that part.
Allison
20 Oct
20 Oct
3:36 a.m.
I am going to impliment the instruction set serially... Hmm.. wonder where
I've seen that before?
I have run out of transistor/old computers to restore so I rfeally liked the
8/S and am going to do some fun stuff with a few hundred flip chips.
And how does one implment the Acc, DE, HL register pairs serially... Still
needs the flipflops. Then there is the matter of the 7level stack x14bits
in the 8008 or the smaller one of the 4004. That's a lot of memory on the
chip in the form of registers/FFs. In the parallel version that stack
with it's 7x14 and pointer register is some 1/5th the total chips area
and ignoring data paths would be a lot of FFs. Older serial machines did
their best to avoid this kind of trap as did the PDP8 series as it's
register intensive. The ALU in reality is if anything the easy part as a
result even though it's not a simple array.
While the PDP-8/S is serial arithmetic there are large sections that are
still parallel like the memory. I may add the 8/S was not so much size
reduction but cost reduction with side effects of some incompatability
with other -8s and signigficant speed reduction.
Look at the MIT/lincoln labs TX-1 and TX-2 for some indications.
Allison
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