Ok. Here is a second thank you. An interesting read.

I especially appreciated he not only offered an opinion - his specific ideas on where the boarder between RISC and CISC was - but then provided an analysis of a bunch of processors based on those criteria and an analysis of the outliers that challenged his criteria. It's a well thought-out and explained opinion that just doesn't happen often on the Internet. I assume from RS/6000, he meant generally the Power gen 1 architecture. And IBM RT/PC he meant ROMP. I'm pretty sure Alpha was well established when he wrote the analysis. Would have been nice to see that included. If I had more time, I'd research it. Maybe SuperH and WE32 as well. Thanks for sharing! +1 -Alan H. On 2019-06-12 13:45, Chuck Guzis via cctalk wrote:

On 6/12/19 1:47 PM, alan--- via cctalk wrote: Is the discussion restricted to microprocessors? --Chuck

On 6/15/19 7:47 AM, Stefan Skoglund wrote: It's difficult to say exactly, because of the constraints on the definition. Or does something have to be RISC only if it came after the definition? One of the issues with much older systems is that register memory was very expensive--and the corollary, of course, is that memory in general was expensive and a bottleneck. So, for example, the IBM 7030, with all of its very advanced architecture, remains out of the picture, because of its single-accumulator architecture. I don't think I'd call a 7090 a RISC architecture, either. There are plenty of early simple-architecture systems, (e.g. IBM 1130) that fail to qualify under the RISC definition because of this. One detail about the CDC 6000 that escapes many people is that there are no condition codes for branches. Given a three-address architecture, there's no "compare" instruction either (absent the CMU add-on). If you want to compare, say, registers X1 and X2 for equality, your code might look like this: IX0 X1-X2 ZR X0,equal-target The peculiar advantage of this is that condition codes don't come into the picture for the purposes of instruction scheduling--one simply uses the normal result reservation mechanism. The "compare" (IX0) above, can be anywhere in the preceding instruction stream before the zero jump. --Chuck

On a related note, a fun talk about ARM https://www.youtube.com/watch?time_continue=2045&v=_6sh097Dk5k

On 6/15/2019 8:47 AM, Stefan Skoglund via cctalk wrote: Well the early 1960's was the rise of BIG IRON that had REAL POWER and that led to people thinking about high level languages and Computer Science in general. We got PL/I (USA) and ALGOL (Every where ELSE) that is a realy hard to compile into effective code. CISC design is now needed to handle the 'extended features'. C was simmpler, but still hand many features. RISC came along only because Compilers could only generate SIMPLE instructions, that matched the RISC format. My 2 cents. Ben.

I'm handling some tapes from the late 60s-early 70s and came across a curious situation. There are many Scotch 701 and 777 tapes in the lot with "yellow" labels, but on the single 777 "blue label" tape, I've encountered binder bleed something fierce. Running a reel through the tape cleaner at low speed leaves a coating of sticky goo on the cleaning blade and the tape where the tape motion stops. Fortunately, the goo can be cleaned off the tape with some 91% isopropanol; the same holds for the cleaner blade. This was with a tape that had spent a day "baking". Of course, there was no way this tape was going to make it through a drive without sticking to the guides or heads. I coated the tape with a film of cyclomethicone and reading was successful without issues. But I'm curious--I thought that a manufacturer's media type number should be the same, no matter when the tape was manufactured. Obviously, this isn't true--there's "yellow" 777 and then there's "blue" 777. Just a word of caution... --Chuck