CPU design at the gate level - test-drb@ccmp.vtda.org

5 Nov 2001

Tony,

Faster as in is sub 150ns are fairly common and cheap.  Whats
problemtic is that the ALU must do about 8-16 different operations
 so that would be at least a 512kN part or larger.

Also 74(ALS,F,AS)381 in the 16 bit or wider range would be hard 
pressed to do better than 50ns even with carry lookahead.

Allison

-----Original Message-----
From: Tony Duell &lt;ard(a)p850ug1.demon.co.uk&gt;
To: classiccmp(a)classiccmp.org &lt;classiccmp(a)classiccmp.org&gt;
Date: Monday, November 05, 2001 7:06 PM
Subject: Re: CPU design at the gate level

...
   How about
programming an EPROM with a lookup
 table to emulate an ALU? 
Sure, if you want one that takes 250ns or so to produce a result (the 
access time of most cheap EPROMS). The 74x181 is going to be rahter 
faster than that, I think.

I have thought about using fast-ish RAMs (cache rams from old PC 
motherboards) as poor-man's programmable logic. It would run at a 
sensible speed, and wouldn't need proprietry programming tools.

-tony