On Tue, 11 Dec 2001 jpero(a)sympatico.ca wrote: That would probably be his cheapest way to attain the speed he wants. <ducks> -- Jeffrey S. Sharp jss(a)subatomix.com

On Wed, 12 Dec 2001, Boatman on the River of Suck wrote: Well, the processor would be attached to support hardware, and the support hardware would be attached to a UNIBUS connector. There's nothing that says this thing has to be PC-compatible. Are you wanting this to go in big, hex-width cards like old UNIBUS cards, or will you be defining a new form factor, connector (compact UNIBUS?), backplane, and card mounting system for your new UNIBUS (UNewBUS?)? -- Jeffrey S. Sharp jss(a)subatomix.com

On Wed, 12 Dec 2001, Boatman on the River of Suck wrote: How would you talk to unibus without the 300 or more wait states that would make the 1G processor speed useless anyways? Unless you can hook real IO devices up to the processor that are of *reasonable* speed, all you have is a 'souped up adding machine' (to quote _Colossus:_ _The_Forbin_Project) -- Pat

On Wed, 12 Dec 2001, Pat Finnegan wrote: What I was planning on doing is doing a custom set of bridge sets to talk to multiple UNIBUSses (way multiple) simultaneously by way of a channelized I/O system transparent to the software. (We are talking multiple years of work). Peace... Sridhar

On Thu, 13 Dec 2001, Greg Ewing wrote: DUMMY MODE ON What little I've read about UNIBUS told me that UNIBUS has no set clock rate, and that the speed of communication between two devices would be the the highest rate that both devices could handle. If you've got nothing but Sridhar-made fast devices on the bus, what stops you from having a UNIBUS operating at say, 33MHz to 100MHz on average? Remember that I currently have approximately zero electrical engineering (or whatever you choose to call it) knowledge. DUMMY MODE OFF -- Jeffrey S. Sharp jss(a)subatomix.com

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Dave is right on that "Jeeeeezus" part. And my eyes popped. At 1Gighurtz, that is squarely in the one or two inches of traces between CPU and one or two chipsets in turn talking to sluggard chipsets for I/O and outside world stuff, cache intergated w/ CPU die itself, outside talking at DDR rate 266MHz DDR or 333Mhz DDR. 60W heat, .18 or .13 microns, 1.7V, very tiny voltage swings for 1 and 0 signaling, and fairly heavy on pipelining. In other words, $$$. This doesn't means lost the game. Far from it. Athlon XP 1900+ or XP 2200+ (AMD plans to release this in spring to keep Intel hopping.) on 266A chipset, DDR ram, SCSI stuff. All you do is finish the emulation and build up a industial i/o PCI card to interface with front panel for i/o, tape i/o etc. Put the actual core stuff in a standard ATX. CPU makers had to kick off the external cache and stuff the smaller cache (often 256K, 128K, 64K or ugh, no cache ala original celerons) into same CPU die when they went past 600MHz. AMD kept with external cache on slot A processor for awhile longer with few higher clocked CPUs but at big penalty in clock by dividing the CPU clock lower than 1/2 for L2 extneral cache. Intel didn't and went directly to coppermine above 600MHz. I really miss the 512K cache bec time and again I find that size is needed for best performance. But both Intel and AMD is already moving to .13 microns to permit small die (to get enough useable dies from one wafer.) with 512K. FYI: Intel already have PIII w/ 512K Tualatin ($$$) and will get revised P4 w/ 512K this spring. Ick. AMD have it in works on 512K athlon, yay. I wish for 1MB athlon seriously. :-I Cheers, Wizard

Chris Kennedy wrote: If you don't mind manual labor, you can get free software. http://members.aol.com/lasicad/index.htm It goes with the fore mentioned book. Prototype fab will be about $30K. ( depends on chip size ). The real problem is the patents / intellectual property of DEC here. -- Ben Franchuk --- Pre-historic Cpu's -- www.jetnet.ab.ca/users/bfranchuk/index.html

Chris Kennedy wrote: This is a top of the head figure. Since I have computer budget of $50 a month I don't check that often for the latest fab prices. I will stick to slow FPGA's for now. That is not to say I would not like my latest and not so great cpu in real silicon. -- Ben Franchuk --- Pre-historic Cpu's -- www.jetnet.ab.ca/users/bfranchuk/index.html PS. Note even doing chip design in slow technology will show the strengths and weakness of a design. Remember too with the massive pipelining that a real instruction could be 1/10 the clock speed. Note I still think the 6800/6500 architecture makes sense than massive pipelining to save a few % in clock cycles.

On Tue, 11 Dec 2001, Boatman on the River of Suck wrote: What about some sort of non-saturating logic, like ECL? I know they have it down to several hundred picosecond propagation times. I'd suspect you can buy it in unmounted dies, so you can cram enough on a board to make it reasonably sized and with short enough traces. Then you get the challenge of cooling it... Richard Schauer rws(a)enteract.com

On Tue, Dec 11, 2001 at 10:33:02PM -0600, Richard W. Schauer wrote: [ECL] Freon immersion cooling like the CRAY 2 has? -- tsch??, Jochen Homepage: http://www.unixag-kl.fh-kl.de/~jkunz/

On Tue, Dec 11, 2001 at 09:48:22PM -0500, Boatman on the River of Suck wrote: Ahhh, there are two possibilities: 1. Sridhar is making a joke. 2. Sridhar has no clue about digital logic circuit design. * Get one of those fancy FPGAs and be satisfied with 200MHz. It will be faster than everything else you can get for less than $$$$$$$. :-) -- tsch??, Jochen Homepage: http://www.unixag-kl.fh-kl.de/~jkunz/ p.s. * I don't have much clue about that, but enough to say that 1GHz is far beyond a home brewn design with todays tools.

On Wed, 12 Dec 2001, Jochen Kunz wrote: Neither, actually. I was thinking somewhere in the $250,000 range. Peace... Sridhar