16 Jun
2008
16 Jun
'08
11:08 a.m.
Date: Sun, 15 Jun 2008 17:22:48 -0400
From: "Roy J. Tellason"
I thought it was the 179x parts that had the data
separator on-chip,
no?
Nope. The 179x require an external data separator, as well as
precomp ciruitry and floppy-interface buffering, as well as requiring
+12 (although the Fujitsu clones need only +5). It's the 279x that
have the internal data separators, but the 1770/72/73 have just about
everything in a neat little 28-pin package. About all you have to
supply is side and unit-select logic, which is easily done with a
write-only latch. Add address decoding logic and you're pretty much
done. DMA not required. This contributed hugely, IMOHO, to their
being popular on a number of low-end "home" computer systems. The
chip handles motor control (e.g. spin-up time from from motor on to
ready, auto motor-off after a certain number of inactive revs), which
the 179x doesn't do.
The 765-based all-in-ones such as the National 8473 and the WD37C65A
are about as hard to obtain and are a little more difficult to
interface to a Z80 (just about require DMA and interrupts to work
right).
Cheers,
Chuck
16 Jun
16 Jun
1:58 p.m.
Chuck wrote:
the 1770/72/73 have just about everything in a neat
little 28-pin package.
[...]
DMA not required.
Whether DMA is required or not has nothing to do with which member of
the 177x/179x/279x/MB88xx family you use. It's determined by whether
you can write tight enough transfer loops to avoid write underruns and
read overruns.
On a 6502 a typical read transfer loop takes a minimum of 22 cycles,
so a 1 MHz 6502 can keep up with 5.25 inch single and double density and
8 inch single density with programmed I/O. 8 inch double-density
requires a faster processor, DMA, or special tricks.
With a Z80 a typical read transfer loop takes a minimum of 52 clocks,
which on a 2 MHz Z80 meets the requirements for all but 8" double density,
which requires a faster processor, DMA, or special tricks.
On either processor, unrolling the loop does not shave off enough cycles
to get to the 8" double density transfer rate.
Note that the read loop has to be capable of reading bytes at about
20% faster than the nominal rate or overruns become likely.
nominal nominal required read loop
format xfer rate byte time byte time
---------- ---------- --------- -------------------
5.25" FM 125 Kbps 64 us 52 us
5.25" MFM 250 Kbps 32 us 26 us
8" FM 250 Kpbs 32 us 26 us
8" MFM 500 Kbps 16 us 13 us
The 765-based all-in-ones such as the National 8473
and the WD37C65A
are about as hard to obtain and are a little more difficult to
interface to a Z80 (just about require DMA and interrupts to work
right).
The 765-based controllers work fine with or without DMA. Again, the
issue is the data rate.
Eric
19 Jun
19 Jun
10:42 a.m.
On Mon, Jun 16, 2008 at 1:58 PM, Eric Smith <eric at brouhaha.com> wrote:
With a Z80 a typical read transfer loop takes a
minimum of 52 clocks,
which on a 2 MHz Z80 meets the requirements for all but 8" double density,
which requires a faster processor, DMA, or special tricks.
Having missed the first part of this discussion, are we limiting ourselves
to a Z80? If not, I'd nominate a Z80A or Z80B.
12:10 p.m.
Eric J Korpela wrote:
On Mon, Jun 16, 2008 at 1:58 PM, Eric Smith <eric
at brouhaha.com> wrote:
for the discussion there is minmally z80a (2.5mhz) for timing for FDC loops.
The faster 4,6,8 and 10mhz parts can solve the issue with brute force speed.
Allison
With a Z80 a typical read transfer loop takes a
minimum of 52 clocks,
which on a 2 MHz Z80 meets the requirements for all but 8" double density,
which requires a faster processor, DMA, or special tricks.
Having missed the first part of this discussion, are we limiting ourselves
to a Z80? If not, I'd nominate a Z80A or Z80B.
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