pdp11/84 PMI memory: What is the problem with Q bus? - test-drb@ccmp.vtda.org

25 Apr 2020

...
  I actually have -B/-C boards, I should plug one in in
QBUS mode, and get my
 QSIC prototype working again (it somehow random failed during the last year,
 and I've been too lazy to debug it), and write a little program to DMA blocks
 in and out, and see what happens to the data. If I get really energetic I
 could throw a 'scope on the bus and look at bus cycles and see if they look
 OK.

 It would be interesting to have some more detail on the failure.

      Noel 
Noel,
   The experiments you describe above would be very interesting! In the accidental tests 
I did using -C boards in an 11/83, RSX booted ok and ran for a good bit but I think
errors
Started to accumulate due to bad DMA writes that either were written to the wrong logical
block
Or the data written was scrambled. When this happened on my BA23 11/83 I scratched my
head
Took the boards to a BA123 11/83 and repeated the mistake. Fortunately I use two SCSI2SD
devices
In each system and leave one identical unit unmounted except during disk to disk backups.
With good memory boards I was able to do a disk to disk restore and recover everything up
to
My last backup. 

...
  And that might make sense: PMI memory responds to the
Q bus just like 
 normal memory. So from a Q bus device perspective it's just boring old 
 memory and thus no speed improvement. What might speed up is if I did 
 memory to memory (VM0:) copies, but with only 2mb running at the moment 
 there's not a lot of time to check for performance differences. 
Chris,
   I think the way that you see the biggest performance improvements in PMI over Q22
memory
Is when you have heavy asynchronous I/O happening at the same time the CPU is compute
bound
And the memory access is not well cached due to the type of programs being run. This is
more
Likely to happen in a busy multi-user environment. RSX has a tool IOX that was developed
to load a
RSX system and simulate multiple users. The CPU can get at memory via the PMI and not be
delayed
Waiting on the Q22 bus. This is particularly helpful with larger block mode Q22 transfers
that don?t cause
CPU memory access delays.

Mark