That's a _very_ interesting question; AFAIK, the documentation doesn't say. If there's a cache miss, of course, there's one memory cycle delay to load it. If the cache hits, though, there's still added gate delays going through the KT11 - perhaps 20-30 or so (to make a complete guess) - at ~10nsec each, that would be an extra 200 nsec per memory cycle. Not insignificant... Well, that might not be trivial - if the boards have ECOs, it may be hard to tell them from the KT11 changes. The sheet which gives the wiring changes for the KA11 backplane _is_ still there - although there are indications on it that the actual machine differs from the prints! Wheee! :-( Noel