On Sun, 22 Jan 2017, Tony Duell wrote: It's not the I/O vs memory mapping that is the problem with treating the data space of the MC146818 and its derivatives as executable code; most processor architectures do not have a dedicated I/O address space anyway. The issue with these chips is indirect addressing, that is that ordinarily they only present a pair of 8-bit registers on the bus they are attached to, one being an address register to select the intended location within the embedded memory and the other being a data window register which only gives access to a single location at a time. Direct linear access to data in these chips can be achieved with a small amount of glue logic, but this is seldom done. I only know of a single line of computers, namely the MIPS processor based DECstation machines, which had such logic so that internal locations of their DS1287 chip appeared linearly in its dedicated MMIO space slot, providing for atomic RMW accesses from the CPU for example. But even there the locations were only mapped onto the least significant byte lane of the 32-bit internal I/O bus, so direct execution would not be possible due to the unpredictable (or at least uncontrollable, e.g. if pull-ups or pull-downs were provided) nature of bit patterns presented in the upper 24 bits of each 32-bit memory word. You'd have to copy data first from the chip's internal RAM to main RAM to execute it, just as it was done by DECstation firmware with some option board code which was contained in 8-bit ROM chips. Maciej