No and yes. Worst case timing for a typical 256kbit EPROM is 150ns but if you know the address will be stable at least 150ns before the data is required then the delay from /OE to valid data can be as little as 40ns. Also if you know which address lines cause the greatest delay then you can avoid switching them and operate the with a worst case delay of about 75ns. I would guess that, with care, 120ns parts could work and that 90ns parts would work in place of 60ns bipolar PROMs. Lee. ________________________________________________________________________ This e-mail has been scanned for all viruses by Star Internet. The service is powered by MessageLabs. For more information on a proactive anti-virus service working around the clock, around the globe, visit: http://www.star.net.uk ________________________________________________________________________