Al Kossow wrote:
Is it known whether that machine "works", for any value of "works"?
Does CHM have any artifacts relating to the earlier 6809-based Mac
prototypes?
Those photos provide a fascinating glimpse into one stage of the early
Mac development.
* It predates the Twiggy drive, and uses a Disk II. Presumably the
logic board does not have the drive speed PWM circuitry. Maybe it
didn't have the type of sound support found in the production model
either, since that was related to the drive speed PWM.
* It uses fewer PALs than the production machine, which seems surprising
since there don't appear to be too many "jelly bean" parts that could
have been absorbed into the additional PALs. Probably the lack of drive
speed PWM (and possibly sound) accounts for part of that.
* It predates the IWM, and uses a discrete version of the Disk II
controller, e.g., with the P6A PROM, LS174 state register, and LS323
data shift register for the state machine. It does not have the
9334/LS259 octal addressable latch used by the Disk II controller, and
most likely uses port pins of the 6522 in place of that. It can't offer
the "synchronous mode" of the IWM, which would have made it difficult if
not impossible for a 68K device driver to support the higher data rate
of the later Twiggy or Sony drives. If they wanted to have
compatibility with Apple II and III disks, which obviously would have
been a huge win during the software development, the controller
circuitry must be modified to run at a divide by eight from the main
oscillator instead of divide by seven, though it would still be off by
4.4%, making interchange marginal unless you also tweaked the drive
motor speed. (The IWM offered choice of 8x for use in the Mac or 7x for
use in the Apple II and Lisa.)
* It predates the RTC chip, so it appears to have no RTC and hence no
"Parameter RAM".
* It has three EPROM sockets rather than two, and although the 28-pin
sockets could accommodate larger capacity EPROMs, the chip is a 2732
(4K*8), which is obviously only large enough to have a boot loader and
maybe a simple monitor or diagnostics. The real software had to be
booted into the 128K of RAM. When this prototype was built, the plan
for the software was probably much less ambitious than what eventually
shipped. At the time, I think 2764 EPROMs (8K*8) weren't yet readily
available. Masked ROMs were usually available at about double the
density of EPROMs, so they might have had in mind to use three 16K*8
ROMs, for a total of 48KB of firmware.
* It uses two 6551 ACIAs for the serial, rather than the 8530 SCC, so it
wouldn't be able to support AppleTalk.
* Despite using the 6551 ACIA rather than the 8530 SCC, it uses the
26LS30 and 26LS32 for level shifting for the serial ports, which seems
like a very unusual choice.
* The mouse connector is on the front rather than the back. This seems
like a good idea; I wonder why it was changed.
* The "Programmer's Switch" is on the back rather than the side.
Possibly the vent holes at the bottom of the sides hadn't been planned yet.
* The connection for the analog board is different. It looks like the
6-pin power connector is probably compatible with the Apple II power
supply, and the other header (J8) is probably for the video signals,
though it is surprising that it would need eight pins for that, unless
it is actually supplying power to the analog board via that connector.
* Like the production 128K Mac, it appears that all of the timing
(except for the RTC, which isn't present) is derived from the single
15.6672 MHz crystal. Given that it is using the 6551 ACIA rather than
the SCC, there has to be a 1.8432 MHz clock (or within a few %) for the
baud rates to be correct. I'd never noticed it before, but the standard
Mac clock frequency of 15.6672 is *exactly* eight times the 1.8432 MHz
needed for the 6551 baud rate generator. That's not a coincidence.
(The SCC in the production Mac can divide down from other frequencies,
so it's not an issue there except at the highest serial rates.) In
hindsight, the 15.6672 MHz figure must have been chosen as something
that would divide exactly to get the desired serial rates, was within
the desired range for the video dot clock, and could be divided down to
suitable frequencies for the disk controller and 68000.
* I wonder what the two pin header (jumper?) J6, between the 68K and the
DRAM, was for?