Paul, What was the timeframe for the MPP? Lee On Fri, Feb 18, 2022 at 6:47 AM Paul Koning via cctalk < cctalk at classiccmp.org> wrote: -- Lee Courtney +1-650-704-3934 cell

If you have a university library nearby go check the old Computer Society archives. I was involved with the Supercomputing conferences in the early 90's (and built the E-commerce system for SC94's registration) and talk of this system has knocked loose a marble in my brain from the late 80's. There might be more documentation in the various proceedings or in the Computer magazines and Transactions on Parallel Computing from the time....

There's an issue of DTJ dedicated to the 9000: http://dtjcd.vmsresource.org.uk/pdfs/dtj_v02-04_1990.pdf On Fri, Feb 18, 2022 at 11:01:40PM +0000, Antonio Carlini via cctalk wrote:

On 2/18/22 13:30, Josh Dersch via cctalk wrote: Maybe, maybe not. Failure to sell may have resulted in scrapping. When I had to get rid of my last big iron vaxen at the University it was made quite clear that if I didn't find them a home in a very short time they would be scrapped. bill

I didn't remember all those details, thanks. There also was an effort at one point to adopt FutureBus in DEC systems. We did a pile of design in the network architecture group to figure out how to handle interrupts and bus cycles efficiently; I don't remember if anything actually shipped with that stuff. paul

On 2/18/22 15:35, Paul Koning wrote: There was a FutureBus I/O subsystem for the AlphaServer 8000 series. It was a qualified, orderable option, but I can't imagine we sold very many (if any). It was done supposedly because the US Navy was standardizing on FutureBus for some application. I vaguely recall DEC made an Ethernet adapter that went on FutureBus, but you would have needed another I/O bus to have a usable system. The native I/O interface on the AlphaServer 8000 (aka TurboLaser) was one or more system bus to "hose" modules, where a "hose" was a pair of cables that provided a 32 bit data path in each direction. The hose connected to a bridge module on the target I/O bus. There was support for XMI, PCI, and FutureBus. -- Gary

paul

On 2022-02-18 8:21 p.m., Mark Linimon via cctalk wrote: The 70's was all low scale tech. I suspect it was the high speed/edge rates more the power that kept ECL from common use. Any other views on this topic. Ben, who only had access to RADIO SHACK in the 70's. PS: Still grumbling about buying life time tubes at a big price, just to see all tubes discontinued a year or two later.

I think there are a number of reasons why ECL was niche technology. One is that TTL was fast enough for most applications. Another is that more people knew TTL, and ECL requires (some) different design techniques. Yet another is that higher levels of integration appeared in CMOS but not ECL. Yet another is that ECL was expensive compared to the alternatives, partly because of the low integration and partly because of the low volume. In the mid-1980s (I think) there was a very interesting project at DEC Western Research Lab to build a custom VSLI ECL processor chip. A lot of amazing design was done for it. One is power and cooling work; it was estimated to consume about 100 watts which in that day was utterly unheard of, by a substantial margin. This was solved by a package with integral heat pipe. Another issue was the fact that ECL foundries each had their own design rules, and they were shutting down frequently. So the CAD system needed to be able to let you specify a design where the fab rules were inputs to the layout algorithms. The design took great advantage of ECL-specific logic capabilities like wire OR or stacked pass transistors. I remember that the CAD system let the designer work at multiple levels in the same chip: at the rectangle level (for memory arrays), transistor level, gate level, and even write some constructs as programming language notations. For example a 64-bit register could be specified as: for (i = 0; i < 64; i++) { transistor-level schematic of a one-bit register } Originally the idea was to use this for a 1 GHz Alpha; I think it ended up being a 1 GHz MIPS processor. Possibly the project was killed before it quite finished. That seems to have been one of the very few examples of ECL going beyond SSI. The physical possibility existed; the economics did not. paul