Michael B. Brutman wrote: it is in the 1984 MOS memory data book under http://bitsavers.org/pdf/ti/_dataBooks the pdf will be replaced once OCRing is finished on it.

I have the data sheet on paper (in a TI memory databook), but I notice that Al has put it on-line, so I don't need to copy it. I've worked on the memory expansion PCB for the HP Integral, which uses this DRAM controller along with 256Kbit DRAMs, and I can describe what was done there... The basic problem is the the TMS4500 only has an 8 stage address multiplexer, providing 8 address outputs to the DRAMs. This is fine for 64K bit chips, but of courseyou need 9 bits for a 256K bit DRAM. So you add an external address multipexer chip (a '157 or '158), the problem is finding the signal to swtich it, since that signal is not brought out of the TMS4500. What HP did was to switch the multiplexer using the CAS output of the TMS4500. One section of the mux provided another address line to the DRAMs, a second section had one input tied high and the other tied low. The output of that followed the select input (and thus the CAS output of the 4500), but with a slight delay (due to the propagation delay of the multiplexer). This was delayed slightly more and used to vide the CAS signal to the DRAMs (the extra delay ensured all address lines had settled before CAS was asserted). I hope that gives you some hints as to what to look for... -tony