outgrowth of : OT: how big would it be? - test-drb@ccmp.vtda.org

21 Oct 1999

Please see embedded comments below.

regards,

Dick

-----Original Message-----
From: Tony Duell &lt;ard(a)p850ug1.demon.co.uk&gt;
To: Discussion re-collecting of classic computers
&lt;classiccmp(a)u.washington.edu&gt;
Date: Thursday, October 21, 1999 12:44 PM
Subject: Re: outgrowth of : OT: how big would it be?

...
 >
> What I'm really after is small RAMs with separate ins and outs, and the
> current generation stuff doesn't seem to address that requirement.  I
guess
...
   I'll have
to use a CPLD or FPGA with RAM inside. 
I never found separate data in and out pins to be particularly useful
(well, not unless the chip was dual-ported...). Can't you use buffers to
link a conventional RAM with bidirectional data pins to your design?

Hitachi made some reasonably fast (15ns, and probably faster) SRAMs until
quite recently. I used the 64K*4 ones in a CCD readout system (don't
ask...), and they worked fine. Not cheap, though.
 RAMs with separate D and Q pins are inherently faster, in that you don't
have the delay of the output buffers to wait out.  Since I want FAST here,
that's important.  What's more, the output buffers then don't have to drive
the input capacitance.  That saves more delay.
...

Of course having a RAM that's too large is not a major problem (other
than cost). You can always tie the address pins low (or whatever). I've
seen this done on commercial boards, presumably either because small RAMs
weren't available, or to simplify the inventory of parts needed.
 That's true unless convenient packaging is an issue, which it could be here.
I'll probably have to use an FPGA and use some of its memory capacity as
RAM.
...

-tony