Interesting architecture. Brain dump follows; forgive inacurracy due to bit-rot in the brain. The 88000 was Motorola's' stab at RISC technology, after deciding (well, being told by customers), that there wasn't much interest in follow-ons to the 68040 (look how few 68060 adopters their were, relatively speaking). It came out in 1988, placing it late compared to the rest of the 1st generation of commercial RISC. Harvard architecture, 32 GP registers, register renaming, pipelined w/ interlocks, on-chip FPU, well defined co-processor interface and later on, superscalar & speculative execution. Later versions, as I recall, also had special bit manipulation instructions designed to manipulate pixel data (distant shades of Intel MMX) with seperate functional units to execute those instructions. All the right buzzwords, and it had very competative integer & FP benchmark numbers (I recall ~17MIPs & ~20MFLOPs @ 20MHz for the 88100, depending on speed). I know they ran at 16.67MHz, 20MHz, 25MHz & 33MHz; not sure about other speeds. It started life as a fairly typical multi-chip Motorola design, which certainly impacted manufacturing costs. There was a core CPU chip (the 88100), then some number of 88200 or 88204 CMMU chips, which provided 16KB or 64KB cache, respectively, and an MMU. Cache had split I+D buses, with a given chip dedicated to one or the other bus. One could use 0 to 8 CMMUs, giving up to 256K+256K I+D cache per CPU. AFAIK, 2 was the most common number, and 3 or more was rare due to cost. I know the BBN TC2000 used 3 per CPU, which gave 32KB I & 16K D cache (or vice versa). I can't recall off the top of my head a machine that used more than 4, though there certainly were some. Someone once told me that an Omron Luna used a single 88200 per processor. I've never seen one, so I can't confirm, nor would I know if it was caching instructions or data. Many folks used just the 88100 CPU for embedded applications. NCD built a bunch of 88k Xterminals sans CMMUs, for example. The later (and much faster) 88110 processor integrated MMU & cache (8k+8k I+D) on chip, much like what happened between the 68020 and the 68030 (well...sans cache to be pedantic). They also added more functional units. There was an 88120 that was planned but never saw the light of day. There was plug-and-play hardware support (e.g. hardware cache coherency mechanism) for up to 4 way multiprocessing, so you saw a lot of 2- and 4-way multis. Spinlocks, etc., were real easy to implement on the 88k. Motorola had a pretty strong ABI spec for SVR3 & SVR4 (88Open), which would have been useful had the chip been more successful. Not that I want to provide the canonical list of 88k machines, but I'm guessing DG sold the most 88000 machines. I personally used a Tektronics XD88, which was a beast performer at the time. Encore built a big 88k multi, as did BBN. There were a lot of MVME-based systems, with various badges. There are a bunch of rare/odd machines as well (the Omron Luna is significant because of it's role in developing Mach). As one poster pointed out, Apple considered using the 88000 (including producing prototype hardware and partially porting MacOS), as did NeXT. In the end, Motorola decided (for many reasons that I won't begin to untangle) to back the IBM PowerPC chip. The rest, as they say, is history. ObObscureHistoricalFootnote: DG apparently ported DG/UX to the SPARC at one point. To return the favor, Sun ported Solaris 2.5 to the PowerPC (the chip that replaced the 88000). Doubtful anyone ever purchased either product. That's how I remember it...I could be wrong... Ken Seefried, CISSP