Yes it?s true but my knowledge is not enough to do it. Maybe you would like to take a look
at schematic?
<http://www.hpmuseum.net/capcha/freecap_wrap.php?r=4020>
The output signal /HPIBGr from pin 18 of the PAL (sheet 17) is stuck at 3 Volts (even
disconnecting the pin to the pcb), consequently the /DPEn signal always remains at logic
level 1, (sheet 12) so the Peripheral Data Bus is never connected to the Processor Data
Bus. (pin /enable 74LS245 IC U54 sheet 12)
I also tested U93 (sheet 12) driving the signal /HPIBGr by a signal injector and is
working.
Obviously trying to read the PAL (which doesn't seem to be protected) I got something
that doesn't make any sense.
Piero
Il giorno 10 giu 2019, alle ore 17:46, dwight
<dkelvey at hotmail.com> ha scritto:
Again, is it just an address decoder or something more complicated. One can often
determine the logic by looking at a schematic and knowing what it needs to do.
Dwight
From: cctech <cctech-bounces at classiccmp.org> on behalf of Piero Andreini via
cctech <cctech at classiccmp.org>
Sent: Monday, June 10, 2019 7:58 AM
To: cctech at
classiccmp.org
Subject: Re: HP9816 PAL16L8 (alan at
alanlee.org)
L series are combinatorial only. You (or someone
who has a working one)
should be able to figure out a logic map by either running through all
the input permutation or putting it in a reader that will do the same
(vs reading the fuse data).
-Alan
Good luck.
unfortunately I don't have a working PAL, that's why I'm looking for the
jedec file