Hi Henk, That's where I just came from when writing the first message. On the second page there's mentioned a pdp-8 core from Hans Pufal. Who is that? Is he still active? If the PDP-8/I thing has already been built with an FPGA, it won't be a problem to try out other cores... That's one of the reasons to use an FPGA :-) What's the current state of pdp-8 implementations on FPGA? Best wishes, Philipp :-) -- http://www.hachti.de

From: "Philipp Hachtmann" <hachti at hachti.de> Sent: Thursday, December 18, 2008 7:31 AM Very cool! Heh, it seems impossible to deal with the hundreds of warnings to figure out which, if any, are important. Hmm...I don't share your need for speed :-). I am more worried about being able to interface with new and old external gear. Vince

Vincent Slyngstad wrote: Last I knew of Hans was about a year ago, but that was news via a third party...

From: "Philipp Hachtmann" Sent: Thursday, December 18, 2008 11:08 AM [good stuff elided] You definitely need the "reset" that the CAF instruction (and the "clear" key on an 8/e triggers). For an 8/i, it's BINITIALIZE, which is triggered by the "start" key on the front panel. The original PDP-8's have these active low, and a logical OR is implemented with wire-and, via open-collector drivers. Cool! It might be an interesting point to work from for what Henk and I are trying to do. VHDL. Most of them -- Skips are never skipping, and all IOTs clear AC. Shouldn't be too hard to fix, but I haven't really looked into it yet. Right. The word "license" doesn't appear in any of the files, and we haven't been able to get a response from him on the subject. I'm hoping to get around that by declaring TP1...TP4 (and *strobe*, etc.) to be the clocks, and re-expressing the latches so that they are clocked by an "official" clock. I don't know yet how well that is working out, as it's buried in with the other 188 warnings-of-the-moment. Vince

Ben, No. That's the price for using arrays of CPLDs. In an FPGA you get waste amounts of logic and very fast RAM. The only hassle is soldering FPGAs. But cheap development boards can be found. Where's the problem? I currently use a VGA front panel (view only) to see what my "machine" is doing :-) So everybody else can do that, too - on an FPGA, of course :-) Apropos "main adder": one thing about my PDP-8 design: It is designed for speed, not for size. So there are a lot of adders - no adder will get it's input switched. I always have a PC+1, PC+2, AC+1, MD+1, etc. Results are selected by multiplexers. Philipp -- http://www.hachti.de

No easy way? It's TOTALLY hassle-free! With Xilinx, you just have to press a few buttons to compile and load your design. Works wonderfully! Many development boards come with USB and Windows software. That's the easiest way. I use a JTAG cable under Linux. Works perfectly. I can program the FPGA or the flash. Hehe :-) I've never used a CPLD... I started with FPGAs. The CPU roughly works as follows: In the first phase, decode, the opcode is already at the output of the RAM. Memory data is wired to the instruction decoder which makes a lot of tiny signals. All those signals are registered afterwards. Subsequent cycles in the same instruction use the registeres variants. Every register has a source select signal (with own VHDL type *g*) and a load enable signal. The state register is always loaded with the "next_state" signal. All control signals including next_state are made in the combinatorial sequencing process - it's a monster! There exist evil things like pc_next, ac_next etc. They're determined by the selector multiplexers. In the last cycle of an operation, load_pc is enabled, memory address source select set to "pc_next". Then, after the clock, the cpu halts in the decode state or continues. On power-on, one fetch cycle is forced, and the CPU halts in decode state as well. With PC loaded and memory data lines containing the instruction. ISZ I needs to store the pointer while it does other things with the memory. The MD register serves only for that purpose. A "true" memory data display like in the old machine would need a little bit of additional logic. But it's not too difficult to build. http://hachti.de/download/major_states.pdf Thanks. I HAVE logic to burn... The CPU with much additional stuff like VGA interface and useless PS/2 mouse interface currently fills about 60% of a Spartan-3 200K chip. The CPU takes (estimated, could have grown) between 20% and 30% of the chip. Most boards nowadays come with 400K, 500K, 1000K or 1200K gates FPGAs... :-) So... Why should I keep it small.... Philipp -- http://www.hachti.de

From: "Philipp Hachtmann" Sent: Thursday, December 18, 2008 10:38 PM You can emulate that in std_logic with a single driver driving an "H" (the "pull-up"), and everyone else drives either "0" or "Z". As an ex-software guy, I find VHDL counter-intuitive and kinda ugly, but it's what Hans used :-). I'm using the Xilinx ISE built in editor. No, I'm trying to re-express everything in a few clock domains, namely the timing pulses at the beginning of the cycle. The rest goes in the combinatorial part of the thing: if (tp4'event and tp4 = '1') then fetch <= f_set; defer <= d_set; execute <= e_set; word_count <= wc_set; current_address <= word_count; break <= b_set; end if; and dozens more like it :-). Yeah, I've seen that. Vince

From: "Philipp Hachtmann" Sent: Thursday, December 18, 2008 11:16 PM The advantage being that you didn't need to round up all the signals and OR them yourself :-). (I believe you do get yet more warnings, though.) Well, that's a matter of perspective, since the end of TS4 is just as easily thought of as the start of TS1. Thus TP4 triggers the setting of TS1 and initiates all the work of TS1. Not sure what the epithet "sequential coding" means in this context. There is combinatoric logic elsewhere computing the new values for these 6 latches, which take their new values at the beginning of TP4. Much of the earlier R/S stuff in the straight-8 feels that way to me. Lots of transistors just being yanked this way and that. Then again, every time I look at the 8/i drawings, they seem more synchronous, so maybe it's just that I haven't fully understood the older machines yet. Vince

Funny, I'd've thought the goal would be to have a working circuit. If minimizing warnings really is your goal, there's a very easy fix. What's the difference? As I've learned to use the words, D-flops _are_ latches. Have I mislearnt? /~\ The ASCII Mouse \ / Ribbon Campaign X Against HTML mouse at rodents-montreal.org / \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B

On 19/12/2008 15:53, der Mouse wrote: They're not quite the same thing, though a D-type flip-flop is a kind of latch. There are other types of flip-flops, such as T, RS, and JK types, usually edge-triggered. In a D-type, the active clock edge causes the output to change to match the input, and having changed, it stays that way, even if the input changes while the clock is still at the same level. The transparent latches that are commonly just referred to as "latches" (eg in data books, where you'll find some devices referred to as latches and others as flip-flops to distinguish them) are level-sensitive, and the output tracks the input (including changes) while the clock is at its active level. -- Pete Peter Turnbull Network Manager University of York

A clocked JK with the JK held high will perform the same function. ----- Original Message ----- From: "Tony Duell" <ard at p850ug1.demon.co.uk> To: <cctalk at classiccmp.org> Sent: Saturday, December 20, 2008 6:10 PM Subject: [personal] Re: PDP-8 on FPGA project & where is Hans Pufal? >> > Your code above does not result in latches. It results in D type >> > flipflops! >> >> What's the difference? As I've learned to use the words, D-flops _are_ >> latches. Have I mislearnt? > > As I understand the terms, a D-type flip-flop is edge-triggered, a latch > (or more exactly a transparent latch) is level-operated. > > What I eman is that for a D-type flip-flop, the output (Q) is set equal > to the input (D) a short time after the rising edge (say), of the clock > signal. At all othter times Q does not change state, no matter what D > does. So if clock is held high all the time, or held low all the time, Q > will never change. > > But with a transparent latch, then if the clock (sometimes called the > enable input) is in one sate (say high). then the output (Q) tracks the > input (D). When the clock input goes low, then Q is held in whatever > state it was in as the clock input went low. > > do the same thing with a transparent latch, you get something that > oscillates at a frequency determined by the propagation delays when the > clock is high. In other words the output is somewhat unpredicatable, it's > certainly not a square wave at half the frequency of the clock signal. > > -tony > > >

On Monday 22 December 2008 04:07:10 am Mike Hatch wrote: As will tying the D input back to not-Q, which most of them have. The advantage to using the D-type over the J-K is two fewer package pins needed, which may or may not be important to somebody. And what the heck does that J-K stand for, anyway? -- Member of the toughest, meanest, deadliest, most unrelenting -- and ablest -- form of life in this section of space, a critter that can be killed but can't be tamed. --Robert A. Heinlein, "The Puppet Masters" - Information is more dangerous than cannon to a society ruled by lies. --James M Dakin

John Kardash invented the JK flip flop. At least, that is what the prof said back in 1982 when I was at school.

Chuck Guzis wrote: http://taracom.net/chip.pl?to=management John Kardash, Sr. Scientist M.S. EE, Temple University Over 30 years of experience in IC design and management. Inventor of JK flip flop. Developed many analog and digital integrated circuits for disk drive market. Holds 17 patents on digital and analog circuits and one patent on phone detection system. John was key designer of the Suhl (Sylvania high logic), which became the Industry TTL line. He has also designed many production worthy circuits for Automotive, Telephone, Disk Drive, and Communication markets.

Chuck Guzis wrote: Earliest real refs I have are in the 1965 TI and 1966 Fairchild catalogs, both list JK flip-flop ICs. They both list JK types in the early RTL families, amongst others. I presume the JK type was introduced as a common building block after the development of ICs, as it's a relatively expensive construct, applications can generally be implemented more optimally when using discrete components. I find the Wiki entry, or it's phrasing, rather weak. The date mentioned (1968) is a date of a letter about the origins of the name and it doesn't say anything about the date of those origins. It's also ambiguous in saying Hughes used only one type of FF and then implies there were 5 types.

I suspect the name was fairly well-established by that point. The HP9100, which came out about a year afterwards, and which used discrete transsitors, contains 2 PCBs of flip-flops. Each PCB cotnains 20 JK flip-flops (and a little clock control circuitry), they are essentially master-slave JK flip-flops built from 4 transistors. The transistors are labelled in the etch of the PCB 'J', 'K', 'E', 'F'. The 'J' and 'K' transitors are for the input flip-flop (and thus, presumabluy, conrrespond to the J and K inputs). The 'E' and 'F' transistors are for the output flip-flop, why they have those names and not, say 'Q' and something-else I don't know. Alas since the only info on the intenrals of the 9100 is that obtained by lookibng at the machine, I doubt I'll ever work out why 'E' and 'F' -tony

From: "Philipp Hachtmann" Sent: Friday, December 19, 2008 6:58 AM Agreed. I stand corrected on the terminology. The part that is being modeled was originally a 7474 edge triggered device, though, so the model seems correct. The real question about correctness would seem to be whether it is safe to refactor the "gated clock" into the combinatorial inputs. Which basically depends, on whether the gating elements are stable by the end of TSn and throughout TPn. Me too, though it's generally getting easier. Basically there are a mess of delay lines which establish the spacing of the major timing signals, with a few delay chains that are conditionally inserted for special (longer) cycles. Vince

Hi, Yes, of course... IOBs can also be controlled "manually" using the output enable... The discussion was about the on-chip (!!) wiring of the OMNIBUS. the original OMNIBUS is an open collector thing. Ph :-) -- http://www.hachti.de

I know the VGA problem... Happens only if I restrict the update to the blanking period... If I don't restrict, I get a slight stranger image, but the real blinkenlight effect :-) -- http://www.hachti.de

Vincent Slyngstad wrote: An emulator I am developing for a machine (Wang 3300) with a front panel would suffer the same problem too. It is really an aliasing problem. You are attempting to sample a 1 MHz signal at 60 Hz, so what do you expect? My solution in the emulator is to compute the ratio of on/off over that 1/60th of a second and then use that to display an image of a lamp. Actually, I go one better than that. I have a simple first order time constant model of the lamp so that it doesn't go from 0->100% in 1/60th of a second. new_intensity = K*old_intensity + (1-K)*new_duty_cycle. Pick K to approximate the thermal inertia of the lamp. Oh, to keep from having to compute a tally of all the lamps after each instruction simulation cycle, I have an array of 256 counters for each byte of address or data bus. So for a given byte, after each instruction I just do: histo[byte_value]++. At the time it comes to display each lamp, I look at all the buckets and figure out the average duty cycle for each of the 8 lamps in the group. Those two solve the sampling problem to a sufficient degree that I'm done tweaking with it.

From: "Jim Battle" Sent: Friday, December 19, 2008 12:47 AM Cool! A great use of the extra memory and MIPS on your emulation host :-). There are probably easily enough resources to do the same thing in the FPGA, though most of the VGA outputs lack enough intensity resolution to render the brightness directly. So you'd have to use the intensity to modify the address given to the character generator, and render it as a different sized dot, or the like. Vince

Vincent Slyngstad wrote: ARGGG!!!!!! **WORMS** Check bitsavers for the hardware manuals for the PDP-8 and the PDP-5 lots of detail in what happens. The problem as I see it is that you are thinking the PDP-8 can have any memory thrown at and it works for realistic state emulation. All the computers of that era is based on the memory cycle of *CORE* memory. <setup address><read><pause><write back> Untill you design your memory around that you will have problems. The PDP 8/e's clock was I think 20MHZ to generate the proper timing for 1.2us memory cycle, I think you could just get by with 5 or 6 clocks per memory cycle. The tricky part is that Memory buffer register is latched with the core data, and then incrimented on the *same* clock. A 100 MHZ FPGA could endup at 20 MHZ but that really depends on the speed of the block ram. Ben.

Ben, Thanks. No docs needed: Bitsavers is well known and I have most of the original docs. Nearly realistic. Not 100% realistic. But it's quite sufficient the way I implemented it. Yes, and my design is based on the memory cycle of block rams :-) My design makes one memory access on EVERY clock cycle. It is a bit pipelined as all operations (execute phase) is layered with next fetch etc. Only IOT operations need two cycles and waste one memory access time. That has been done because I wanted to give a bit relief to the decode state logic. Why should I? My (first) design has passed the MAINDEC acceptance tests and runs original software. The improved design is still being debugged and enhanced. I do one clock per memory cycle. But an ISZ instruction takes at least three cycles. That's the only instruction where my design is really slower than the original. ISZ I plus auto-increment is currently the longest instruction. I know. It's done nearly that way. No. Currently I run 100Mhz CYCLE frequency. The block RAM can virtually has no speed limit on FPGAs. To be clear: My PDP-8 currently does 50000000 additions/second. Or 100000000 operate or jump instructions/second. Best wishes, Philipp -- http://www.hachti.de

There's ONE problem: SIMH on a modern PC runs MUCH faster! Hm... Ok. When I turn on a real PDP-8, 1200ns is normal. But today... I have much more gate delays: The times are only the synthesis estimates! In reality, it gets other timings (currently it wants 17ns - but runs with 10 *g*) 20ns per stage? Ok, I understand... ?? There are other packages :-) Xilinx Spartan-II, Spartan-3 and Spartan-3e at least can be found in handy 144 pin packages. They *can* be soldered manually. It's easier than everybody thinks. BGAs are quite impossible... And all the bigger Chips (>400k) are only available in BGA package :-( Philipp :-) -- http://www.hachti.de