On 12/07/2014 11:25 AM, Noel Chiappa wrote:
From: Jon
Elson
Power the system off for 10 minutes, then power
on and read various
locations. If data bit 4 shows 1's and 0's, then the reading is OK, and
it is the writing path that is stuck.
I'm not sure this will work, as the anomalous voltage I see (2V) is after the
output (i.e. to the QBUS) data latches, but before the bus transceiver: i.e.
in the output (reading) path. So I know it's the output data path that has a
problem, not the input.
Output from the memory chips? Well, then, you may have to
replace them all, as one chip may be jamming the bus. Do any
of the affected driver chips run hotter than the others? That's
the "finger test", you replace any anomalously hot chips first,
then replace any others that are tied to lines with bad TTL levels,
then you have to go to serious debugging methods.
The only question is which of three chips on the
output data path might be
the cause of the problem; one of the two three-state latches (one for memory
data, one for CSR data), or the bus transceiver. As far as I can tell, those
are the only three devices attached to that conductor (where I see the
constant 2V).
The 2V level sounds like maybe NO chip is driving that node. A shorted
output (or input) would likely pull one way or the other, 2V is about
the resting point of a TTL input.
Jon