5 Sep
2016
5 Sep
'16
11:59 a.m.
For some time I have slowly been working on restoring our PDP-8 to
operating condition.
Here are some notes on the progress:
http://www.datormuseum.se/computers/digital-equipment-corporation/pdp-8
It is sort of working now after reforming capacitors in the PSU, adjusting
memory currents and replacing a 2N3639 in a MA, MB, PC (R211) board.
But bit seven is still showing a 0 when trying to set it. I found an old
note that I wrote somewhere in 1990 that indicated the same problem was
present then as well so it hasn't happen lately.
I have now concluded that the fault is in the core memory module itself.
The sense winding is broken on bit plane 7.
So what are my options?
What are the chances that a repair is successful? It looks really complex
to take it appart and get to to layer seven. Then to find the broken wire,
somehow replace it and splice it together with the rest of the sense
winding... Not an everyday job.
Does anyone have a known good spare module? I have some MM15 modules for
PDP-15 to trade with!
Could a MM15 module be adapted to be used instead? It is completely
different foot print and it is a three wire stack.
The Russian stacks sold on Ebay? But what guarantees are that those work at
all and can be adapted... Probably other memory currents and cycle time?
Some other technology that can be used to make up for the missing bit
plane. But what technology and how. With as little intrusion in the
machine. I don't really want to replace the entire memory system with a
battery backed SRAM...
Any ideas, thoughts or a working PDP-8 core memory module is highly sought
for!
/Mattis
5 Sep
5 Sep
2:21 p.m.
On 09/05/2016 01:59 PM, Mattis Lind wrote:
I have now concluded that the fault is in the core memory module itself.
The sense winding is broken on bit plane 7.
Have you actually ohmed out the sense/inhibit wire? There
were some very old memories that had some kind of
metallurgical problem where the wires corroded away, but not
heard of DEC cores being prone to that.
3D core stacks have combined sense/inhibit wires, and there
is usually a pulse transformer between the sense amp/inhibit
driver and the wire itself. Also, if the bit 7 inhibit
driver has a blown transistor, it could cause the sense amp
to be shunted or overloaded. I'd check all the associated
sense/inhibit circuitry before assuming it is the plane.
(Of course, you may have already done all this by swapping
boards, etc.) A blown inhibit driver could take out the
pulse transformer, too.
Jon
3:26 p.m.
m?ndag 5 september 2016 skrev Jon Elson <elson at pico-systems.com>:
On 09/05/2016 01:59 PM, Mattis Lind wrote:
>
> I have now concluded that the fault is in the core memory module itself.
> The sense winding is broken on bit plane 7.
>
>
> Have you actually ohmed out the sense/inhibit wire?
Yes. I have measured at at the tabs where the red arrow points in the image
below:
http://i.imgur.com/x5VVh2F.jpg
Unfortunately I am pretty sure that this will rule out pulse transformers
or whatever.
/Mattis
3:39 p.m.
On 09/05/2016 05:26 PM, Mattis Lind wrote:
m?ndag 5 september 2016 skrev Jon Elson <elson at
pico-systems.com>:
Ugh! That could be messy. DEC later went to planar
memories, for obvious reasons. Yes, these built-up core
stacks could be hard just to open up to get to a single
plane. IBM, CDC and others all made them like this in the
60's before realizing how hard that made the job of testing
and repairing. (I guess the shrinking of the cores is what
really made the planar core boards practical.) Well, unless
there is a spare plane in the stack, you can't break it too
much more than it is broken now! But, really, if one of the
wires has failed within the plane, it could be just about
impossible to fix. If it is a break outside of the core
matrix, that wouldn't be hard to fix, unless the wires have
become brittle over time, in which case any manipulation
would just cause more damage. GOOD LUCK!
Jon
Jon
On 09/05/2016 01:59 PM, Mattis Lind wrote:
> I have now concluded that the fault is in the core memory module itself.
> The sense winding is broken on bit plane 7.
>
>
> Have you actually ohmed out the sense/inhibit wire?
Yes. I have measured at at the tabs where the red arrow points in the image
below:
http://i.imgur.com/x5VVh2F.jpg
Unfortunately I am pretty sure that this will rule out pulse transformers
or whatever.
3:46 p.m.
m?ndag 5 september 2016 skrev Jon Elson <elson at pico-systems.com>:
On 09/05/2016 01:59 PM, Mattis Lind wrote:
This is by the way a four wire stack. Separate sense and inhibit wire.
Come to think of it, since the inhibit wire is OK, would it be possible to
arrange it as a three wire stack somehow. Change the sense amp and inhibit
drivers so that they use the same wire?
Maybe Brent can come in with some advice if this is possible or just
stupid. I promise to read his excellent article on core memories once again
tomorrow when I am less tired to see If I can figure something out...
I have now concluded that the fault is in the core memory module itself.
The sense winding is broken on bit plane 7.
Have you actually ohmed out the sense/inhibit wire?
4:36 p.m.
On 09/05/2016 05:46 PM, Mattis Lind wrote:
m?ndag 5 september 2016 skrev Jon Elson <elson at
pico-systems.com>:
OH! I didn't know any PDP-8 had
4-wire planes. Very
interesting. Hmmm, you could rig a pulse transformer to the
inhibit wire to bring signals over to the sense amp.
On 09/05/2016 01:59 PM, Mattis Lind wrote:
> I have now concluded that the fault is in the core memory module itself.
> The sense winding is broken on bit plane 7.
>
>
> Have you actually ohmed out the sense/inhibit wire?
This is by the way a four
wire stack. Separate sense and inhibit wire. Come to think of it, since the inhibit wire is OK,
would it be possible to
arrange it as a three wire stack somehow. Change the sense amp and inhibit
drivers so that they use the same wire?
Ah, you already thought of that. Well, it
SHOULD be
possible. You'd probably put a resistor in series with the
pulse transformer so that all the select current went
through the inhibit wire. Then, the only problem would be
that the sense amp gets hit with a big pulse during the
writeback. As long as the sense amp recovers from the
overload before the next read cycle, it ought to work. Some
4-wire planes were set up so the polarity of half the sense
wires were opposite to the inhibit, so the coupled inhibit
current balanced out to zero in the sense winding. Any
mid-sized 1:1 pulse transformer should do the coupling, the
currents might be pretty high, but the duration isn't very
long. (Minor nit, the inhibit wires only get pulsed one
direction, so you might need a resistive path across the
secondary to discharge the flux build up so it doesn't
saturate.)
Maybe Brent can come in with some advice if this is
possible or just
stupid.
It is NOT stupid, I think it could really work!
Jon
7:28 p.m.
On 2016-Sep-05, at 4:36 PM, Jon Elson wrote:
On 09/05/2016 05:46 PM, Mattis Lind wrote:
I'd tend to be more pessimistic about this working.
There are different requirements in winding a wire for purposes of inhibit and sense.
In the 3-wire arrangement the winding of the combined wire has to meet both
sets of requirements.
Specifically, for this case, in a 4-wire mem, where the inhibit wire was woven just for
the purposes of inhibit, I don't anticipate it's going to have the noise
cancellation topology
needed to function as the sense wire.
Sense wires were woven as a floating loop feeding a differential amplifier. The loop is
kept
quite closed or otherwise woven in a very balanced manner so that the magnetic fields from
the
large select currents (and other influences) will cancel out or be rejected as common-mode
influence at the
differential amp inputs.
The select current magnetic fields trigger the magnetic field reversal of the core, you
want to sense the latter distinct from the former.
Unless you have circuitry with the wherewithal to distinguish those induced currents in
the sense wire in time
(delay of the core field reversal from the select field), you otherwise have to minimise
the influence of the select current fields on the sense wire.
If you look at the diagrams in my article you can see the sorts of differences in weaving
topologies between 3 & 4 wire arrangements,
as well as examples of the tortured topologies resorted to to balance the sense loop.
In the 3-wire example there you can see how the S/I wire was split in half with a special
resistor network at one end to allow inhibit current flow
while at the same time configuring it as a balanced loop for the sense function.
My article certainly isn't the last word on the variety of implementations, I believe
there were 4-wire designs with sense wires parallel to
select wires as in the 3-wire designs for example, so you never know until you examine the
specifics at hand,
but I think it unlikely you'd have much success getting the inhibit wire to function
for sense, not without going to as much trouble
messing with the stack as if you tried to fix the sense wire.
If the sense wire is open I'd guess there's a good chance it's at one of the
end points where it's soldered to a terminal or at an existing splice
m?ndag 5 september 2016 skrev Jon Elson <elson
at pico-systems.com>:
OH! I didn't know any PDP-8 had
4-wire planes. Very interesting. Hmmm, you could rig a pulse transformer to the inhibit
wire to bring signals over to the sense amp.
On 09/05/2016 01:59 PM, Mattis Lind wrote:
> I have now concluded that the fault is in the core memory module itself.
> The sense winding is broken on bit plane 7.
>
>
> Have you actually ohmed out the sense/inhibit wire?
This is by the way a four
wire stack. Separate sense and inhibit wire. Come to think of it, since the inhibit wire is
OK, would it be possible to
arrange it as a three wire stack somehow. Change the sense amp and inhibit
drivers so that they use the same wire?
Ah, you already thought of that. Well, it
SHOULD be possible. You'd probably put a resistor in series with the pulse transformer
so that all the select current went through the inhibit wire. Then, the only problem
would be that the sense amp gets hit with a big pulse during the writeback. As long as
the sense amp recovers from the overload before the next read cycle, it ought to work.
Some 4-wire planes were set up so the polarity of half the sense wires were opposite to
the inhibit, so the coupled inhibit current balanced out to zero in the sense winding.
Any mid-sized 1:1 pulse transformer should do the coupling, the currents might be pretty
high, but the duration isn't very long. (Minor nit, the inhibit wires only get pulsed
one direction, so you might need a resistive path across the secondary to discharge the
flux build up so it doesn't saturate.)
Maybe Brent can come in with some advice if this
is possible or just
stupid.
It is NOT stupid, I think it could really work! from manufacture time and might be repairable if access
could be had.
Might the stack have a parity bit array that could be redirected to replace the faulty bit
array?,
perhaps foregoing the parity checking on that board-set if the parity logic is present.
8:03 p.m.
On 09/05/2016 09:28 PM, Brent Hilpert wrote:
I'd tend to be more pessimistic about this working.
In the 3-wire example there you can see how the S/I wire was split in half with a special
resistor network at one end to allow inhibit current flow
while at the same time configuring it as a balanced loop for the sense function.
My article certainly isn't the last word on the variety of implementations, I believe
there were 4-wire designs with sense wires parallel to
select wires as in the 3-wire designs for example, so you never know until you examine
the specifics at hand,
but I think it unlikely you'd have much success getting the inhibit wire to function
for sense, not without going to as much trouble
messing with the stack as if you tried to fix the sense wire.
Well, older core
memories had larger cores, which slowed
everything down as well as gave much bigger pulses when a
core flipped. That might make this exercise a bit easier.
If the sense wire is open I'd guess there's a
good chance it's at one of the end points where it's soldered to a terminal or at
an existing splice
from manufacture time and might be repairable if access could be had.
But, he has
to split the whole stack to at least access the
bad plane from one side. Already a pretty daunting
exercise. Still, fixing the bad wire, if the break is at an
exposed point, would be preferable than re-engineeering the
whole sense-inhibit circuitry. If the wire can be fixed,
there would be no engineering required.
I saw our old IBM 7094 memory, which had a combination of
tube and transistor circuitry, and one inhibit (or maybe
sense) wire had been burned up by a failed circuit. The
cores kept the wire cool, so the only places it opened was
where the wire looped around the plane. There were dozens of
bits of wire soldered to fix the places where it opened.
Sheesh, I sure wouldn't have wanted to be the CE who had to
do that repair!
Jon
6 Sep
6 Sep
2:11 a.m.
I'd tend to be more pessimistic about this working.
There are different requirements in winding a wire for purposes of inhibit
and sense.
In the 3-wire arrangement the winding of the combined wire has to meet both
sets of requirements.
Specifically, for this case, in a 4-wire mem, where the inhibit wire was
woven just for
the purposes of inhibit, I don't anticipate it's going to have the noise
cancellation topology
needed to function as the sense wire.
Sense wires were woven as a floating loop feeding a differential
amplifier. The loop is kept
quite closed or otherwise woven in a very balanced manner so that the
magnetic fields from the
large select currents (and other influences) will cancel out or be
rejected as common-mode influence at the
differential amp inputs.
The select current magnetic fields trigger the magnetic field reversal of
the core, you want to sense the latter distinct from the former.
Unless you have circuitry with the wherewithal to distinguish those
induced currents in the sense wire in time
(delay of the core field reversal from the select field), you otherwise
have to minimise the influence of the select current fields on the sense
wire.
If you look at the diagrams in my article you can see the sorts of
differences in weaving topologies between 3 & 4 wire arrangements,
as well as examples of the tortured topologies resorted to to balance the
sense loop.
In the 3-wire example there you can see how the S/I wire was split in half
with a special resistor network at one end to allow inhibit current flow
while at the same time configuring it as a balanced loop for the sense
function.
My article certainly isn't the last word on the variety of
implementations, I believe there were 4-wire designs with sense wires
parallel to
select wires as in the 3-wire designs for example, so you never know until
you examine the specifics at hand,
but I think it unlikely you'd have much success getting the inhibit wire
to function for sense, not without going to as much trouble
messing with the stack as if you tried to fix the sense wire.
Thanks. I think that this information will rule out the idea of using the
inhibit wire instead. It is likely to be not viable.
If the sense wire is open I'd guess there's a good chance it's at one of
the end points where it's soldered to a terminal or at an existing splice
from manufacture time and might be repairable if access could be had.
Access is of course the problem. I tried to check at the terminals and it
looked like the wire was ok there, but it is in an extremely tight place. I
tried to apply some small amount of solder in the hop that it was just bad
contact at one of the terminals but no difference unfortunately.
Might the stack have a parity bit array that could be redirected to
replace the faulty bit array?,
perhaps foregoing the parity checking on that board-set if the parity
logic is present.
I think I have checked the existence of a parity plane. It appears that
there is none present. The writing on the core module show no parity plane
and there are only twelve sense and inhibit terminals.
So what are the other options?
* Trying to repair the unit. Every plane is soldered together with the ones
nearby to convey the X/Y signals. This can probably be undone with a
patience and soldering braid. But what are the chance that the X/Y wires
gets lose then? Are those soldered or welded into place?
Then it would be quite tricky to just identify where it is actually broken.
Any ideas for how to do this? A microscope of course. Any other ideas?
Applying an electrical field between the wire and something else and try to
detect it?
Repair. If the wire is broken in the mat it is probably not to difficult to
pull out the broken parts. But then the new wire has to be spliced in. What
is t he best technique to do that?
How to push in the new wire in the matrix? I now that Anders was able to do
this with a broken X-wire in a PDP-8/L stack.
* Use a PDP-15 MM15 stack and sense/inhibit boards.
I have several off these. Adding a small backplane, put the X/Y drivers,
sense amp/inhibit drivers and level converters there and then adapt to the
existing slots for the memory module. It would be a horrible mixture of TTL
and transistors. But it would still be core memory.
* Use solid state technology. Possibly inside the memory box so it looks
real but emulates the actual core memory module.
Any ideas how this could be done in the best way?
/Mattis
6:41 a.m.
From: "Mattis Lind: Tuesday, September 06, 2016 2:11 AM
* Use a PDP-15 MM15 stack and sense/inhibit boards.
I have several off these. Adding a small backplane, put the X/Y drivers,
sense amp/inhibit drivers and level converters there and then adapt to the
existing slots for the memory module. It would be a horrible mixture of TTL
and transistors. But it would still be core memory.
There's a guy on eBay who periodically offers stacks for 8/I or 8/L:
http://www.ebay.com/itm/172295154098
Those might (or might not) be more straight-forward to interface (though
DEC's proof of concept is a TTL interface).
* Use solid state technology. Possibly inside the
memory box so it looks
real but emulates the actual core memory module.
Any ideas how this could be done in the best way?
I did some (theoretical) work on a core replacement for the 8/S
a few years ago based on some ideas from John Price. That's
embedded in the "memory" drawing in
http://svn.so-much-stuff.com/svn/trunk/Eagle/projects/DEC/PDP8S/.
(See sheet 2; most of the schematic is just the schematic of an 8/S.)
Somewhere I also explored a notion of pulling the inhibit driver
and sense amp stuff, replacing the stack itself with a memory board,
then replacing the inhibit drivers and sense amps with interface
boards that knew how to talk to the new memory board. If I recall,
that was in the 8/I or 8/L context, though.
I never built any of it, it was just a thought exercise. There seemed
to be plenty of board real estate to work with, though.
Vince
3029
days inactive
3030
days old
9 comments
4 participants
participants (4)
-
elson＠pico-systems.com -
hilpert＠cs.ubc.ca -
mattislind＠gmail.com -
v.slyngstad＠frontier.com