IIRC, since this a.m. when I was reading some of thei XILINX literature, the 'C' in CLB is for CONFIGURABLE though it is complex. It's a RAM lookup table with some gating and a register or two, depending on the type, and has MUCH more configurability, due to the very general functional nature of the RAM lookup table, than most of what you could have made up in a modular fashion using elementary devices like bipolar transistors or mosfets. Nevertheless, getting software to manage the interconnections for you might not be so difficult. I, for example, would make up a symbol in OrCAD for the logic block and then interconnect them in a schematic. Afterward, I would run a netlist in "wirelist" format, which would then describe, net by net, what the specified interconnections are. If I were to want a picture of the interconnection, I'd netlist the thing for the PCB router and have it route them, perhaps optimizing my physical arrangement in the process. If you extend the FPGA logic plock concept a little bit, you can look at its CLB as a 2-bit registered full-adder, in some cases with fast carry logic. It could also be looked upon as a 2-bit registered ALU. Plugging in an ALU for every gate in a design might be inefficient as can be, but by taking advantage of the economy of scale, it could well be realistic in sufficient quantity. That's certainly what XILINX and others have found. Dick From: Chuck McManis <cmcmanis(a)freegate.com> To: Discussion re-collecting of classic computers <classiccmp(a)u.washington.edu> Date: Friday, October 22, 1999 1:27 PM Subject: More on "discrete" CPUs