23 Nov
2015
23 Nov
'15
6:47 p.m.
[Yahoo's webmail client garbled the last link -- resending]
The revived 2013 re-issue of Niklaus Wirth's Oberon system is a joy to behold.? If
you've never heard of Oberon before, it is a minimalistic education-oriented language
and operating system designed after Wirth had taken a (second) sabattical at PARC in the
80's.
The new version runs on a custom RISC processor, implemented in an FPGA, instead of the
NS3032 in the orginal Ceres workstations.?? Originally, it required a Digilent
"Spartan 3 Starter Kit" with a custom-built daughterboard providing a few
additional connectors.? This board is no longer made, however, and no other FPGA
development board appears to provide the 32-bit wide fast SRAM the Oberon CPU required.
Recently, a new board, the OberonStation,? has come onto the market that was designed
specifically for Oberon, and will boot up Oberon 2013 out of the box.?? It also looks like
an excellent platform for other retro-style FPGA CPU designs that want to stay away from
complex SDRAM controllers and the caches they like to feed.
My OberonStation arrived a couple of days ago, and it's really amazing to see what can
be done with a hardware and software stack that is small enough to actually read and
understand.
https://www.inf.ethz.ch/personal/wirth/
http://www.projectoberon.com/
http://oberonstation.x10.mx/
23 Nov
23 Nov
7:11 p.m.
The new version runs on a custom RISC processor,
implemented in an FPGA, ins$
Is the FPGA documented? Or is it yet another "run this binary-only
(and usually Windows-only) program to get an undocumented blob to feed
to the hardware" FPGA? I've been semi-looking for the former for quite
some time, to no avail so far.
/~\ The ASCII Mouse
\ / Ribbon Campaign
X Against HTML mouse at rodents-montreal.org
/ \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B
7:50 p.m.
There is reputedly an open-source toolchain for the Lattice ICE40, based on
reverse-engineering the bitstream:
http://hackaday.com/2015/05/29/an-open-source-toolchain-for-ice40-fpgas/
Industry leaders Xilinx and Altera remain closed as always.
--Bill
From: Mouse <mouse at Rodents-Montreal.ORG>
To: cctalk at classiccmp.org
Sent: Monday, November 23, 2015 7:11 PM
Subject: Re: Project Oberon and OberonStation (resend)
The new version runs on a custom RISC processor,
implemented in an FPGA, ins$
Is the FPGA documented?? Or is it yet another "run this binary-only
(and usually Windows-only) program to get an undocumented blob to feed
to the hardware" FPGA?? I've been semi-looking for the former for quite
some time, to no avail so far.
/~\ The ASCII??? ??? ??? ??? ? Mouse
\ / Ribbon Campaign
X? Against HTML??? ??? mouse at rodents-montreal.org
/ \ Email!??? ? ? 7D C8 61 52 5D E7 2D 39? 4E F1 31 3E E8 B3 27 4B
24 Nov
24 Nov
11:37 a.m.
Just in case anyone wonders, the Oberonstation uses a Xilinx XC3S700AN
aka Spartan-3 FPGA.
So far, I haven't found anything that says that the code for the FPGA
is open source / documented.
Ok, scratch that, I was looking at the http://oberonstation.x10.mx/ site.
Over at http://www.projectoberon.com/ there are a link to
"OberonStation Verilog Source" which is a zip file.
There is a readme file which describes how to build this with the
Xilinx tools too.
Nice.
--
Regards,
Torfinn Ingolfsen
1:13 p.m.
New subject: Open FPGAs? - was Re: Project Oberon and OberonStation (resend)
On 2015-11-24 2:37 PM, Torfinn Ingolfsen wrote:
Just in case anyone wonders, the Oberonstation uses a
Xilinx XC3S700AN
aka Spartan-3 FPGA.
So far, I haven't found anything that says that the code for the FPGA
is open source / documented.
I think mouse was referring to the toolchain, structure of and interface
to the FPGA itself, etc. I.e. an open FPGA product.
--Toby
Ok, scratch that, I was looking at the
http://oberonstation.x10.mx/ site.
Over at http://www.projectoberon.com/ there are a link to
"OberonStation Verilog Source" which is a zip file.
There is a readme file which describes how to build this with the
Xilinx tools too.
Nice.
1:42 p.m.
New subject: Open FPGAs? - was Re: Project Oberon and OberonStation (resend)
> So far, I haven't found anything that says
that the code for the
> FPGA is open source / documented.
(I assume there's a "not"
missing after the "is")
I think mouse was referring to the toolchain,
structure of and
interface to the FPGA itself, etc. I.e. an open FPGA product.
Yes. I consider it important for the custom CPU's definition to be
open. But that's not what I was really interested in; I haven't used
Oberon and don't really expect to start.
What I was really interested in was whether the FPGA itself was open.
If so, I definitely would have wanted to pick up the hardware, because
I would love to experiment with an FPGA - but I am _not_ going to put
up with running a vendor binary blob (which probably won't even run on
my machines) to get an undocumented blob to throw at the hardware.
/~\ The ASCII Mouse
\ / Ribbon Campaign
X Against HTML mouse at rodents-montreal.org
/ \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B
5:20 p.m.
New subject: Open FPGAs? - was Re: Project Oberon and OberonStation (resend)
On 11/24/2015 2:42 PM, Mouse wrote:
What I was really interested in was whether the FPGA
itself was open.
If so, I definitely would have wanted to pick up the hardware, because
I would love to experiment with an FPGA - but I am _not_ going to put
up with running a vendor binary blob (which probably won't even run on
my machines) to get an undocumented blob to throw at the hardware.
I don't see much of a problem, as long as source is portable.
Sadly that is not true anymore as 99% of the designs use ROM/RAM or
other features that of NOT portable.
Ben.
6 Dec
6 Dec
7:39 a.m.
New subject: Open FPGAs? - was Re: Project Oberon and OberonStation (resend)
On 24 November 2015 at 22:42, Mouse <mouse at rodents-montreal.org> wrote:
What I was really interested in was whether the FPGA
itself was open.
If so, I definitely would have wanted to pick up the hardware, because
I would love to experiment with an FPGA - but I am _not_ going to put
up with running a vendor binary blob (which probably won't even run on
my machines) to get an undocumented blob to throw at the hardware.
I don't think that exists, or if it does it must be pretty obscure.
Certainly not Altera, Xilinx (which is used for OberonStation) or
Lattice, and I doubt Microsemi, Actel, or any of the smaller
commercial FPGA vendors have open FPGAs, or even open tools.
CONFIDENTIALITY
This e-mail and any attachment contain KONGSBERG information which may be
proprietary, confidential or subject to export regulations, and is only meant
for the intended recipient(s). Any disclosure, copying, distribution or use is
prohibited, if not otherwise explicitly agreed with KONGSBERG. If received in
error, please delete it immediately from your system and notify the sender
properly.
2:10 p.m.
New subject: Open FPGAs? - was Re: Project Oberon and OberonStation (resend)
On 12/6/2015 8:39 AM, Tor Arntsen wrote:
On 24 November 2015 at 22:42, Mouse <mouse at
rodents-montreal.org> wrote:
> What I was really interested in was whether the FPGA itself was open.
> If so, I definitely would have wanted to pick up the hardware, because
> I would love to experiment with an FPGA - but I am _not_ going to put
> up with running a vendor binary blob (which probably won't even run on
> my machines) to get an undocumented blob to throw at the hardware.
I don't see that as a problem. Treat it like a rom image.
What is a problem old FPGA's vanish just once you get the hardware debugged.
Now back to debugging my FPGA cpu ( Altera DE1 ).
Ben.
2:48 p.m.
New subject: Open FPGAs? - was Re: Project Oberon and OberonStation (resend)
There's one open FPGA toolchain out there, and it's for Lattice iCE40 FPGAs.
http://www.clifford.at/icestorm/
David
Sent from my iPhone
On Dec 6, 2015, at 5:10 PM, ben <bfranchuk at
jetnet.ab.ca> wrote:
On 12/6/2015 8:39 AM, Tor Arntsen wrote:
> On 24 November 2015 at 22:42, Mouse <mouse at rodents-montreal.org> wrote:
>
> What I was really interested in was whether the FPGA itself was open.
> If so, I definitely would have wanted to pick up the hardware, because
> I would love to experiment with an FPGA - but I am _not_ going to put
> up with running a vendor binary blob (which probably won't even run on
> my machines) to get an undocumented blob to throw at the hardware.
I don't see that as a problem. Treat it like a rom image.
What is a problem old FPGA's vanish just once you get the hardware debugged.
Now back to debugging my FPGA cpu ( Altera DE1 ).
Ben.
23 Nov
23 Nov
7:59 p.m.
New subject: Altera Quartus - was Re: Project Oberon and OberonStation (resend)
On 2015-11-23 10:11 PM, Mouse wrote:
Although not always. It's gratifying to see Altera Quartus runs on Linux.
--Toby
The new
version runs on a custom RISC processor, implemented in an FPGA, ins$
Is the FPGA documented? Or is it yet another "run this binary-only
(and usually Windows-only) program to get an undocumented blob to feed
to the hardware" FPGA? I've been semi-looking for the former for quite
some time, to no avail so far.
/~\ The ASCII Mouse
\ / Ribbon Campaign
X Against HTML mouse at rodents-montreal.org
/ \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B
9:19 p.m.
New subject: Altera Quartus - was Re: Project Oberon and OberonStation (resend)
On 11/23/2015 09:59 PM, Toby Thain wrote:
Although not always. It's gratifying to see Altera Quartus
runs on Linux.
Xilinx Ise also has run on Linux for at least 5 years now.
The webpack version is free, and supports up to fairly large
devices.
Jon
7:18 p.m.
Perhaps Oberon required something faster than the 70ns - 85ns tRC read
cycle / tWC write cycle times supported by the Micron cellular RAM
running in asynchronous mode on the Nexys 2 - presumably because the
data path is only 16 bits?
That said, most "retro" computing would, I expect, be perfectly happy
with that kind of cycle time and bus width, yes? And the implementation
in this asynch. mode is very very easy - classic SRAM interface signals.
Looks like the Nexys 3 and Nexys 4 boards have cellular RAM like this as
well.
JRJ
On 11/23/2015 8:47 PM, William Maddox wrote:
[Yahoo's webmail client garbled the last link --
resending]
The revived 2013 re-issue of Niklaus Wirth's Oberon system is a joy to behold. If
you've never heard of Oberon before, it is a minimalistic education-oriented language
and operating system designed after Wirth had taken a (second) sabattical at PARC in the
80's.
The new version runs on a custom RISC processor, implemented in an FPGA, instead of the
NS3032 in the orginal Ceres workstations. Originally, it required a Digilent
"Spartan 3 Starter Kit" with a custom-built daughterboard providing a few
additional connectors. This board is no longer made, however, and no other FPGA
development board appears to provide the 32-bit wide fast SRAM the Oberon CPU required.
Recently, a new board, the OberonStation, has come onto the market that was designed
specifically for Oberon, and will boot up Oberon 2013 out of the box. It also looks like
an excellent platform for other retro-style FPGA CPU designs that want to stay away from
complex SDRAM controllers and the caches they like to feed.
My OberonStation arrived a couple of days ago, and it's really amazing to see what
can be done with a hardware and software stack that is small enough to actually read and
understand.
https://www.inf.ethz.ch/personal/wirth/
http://www.projectoberon.com/
http://oberonstation.x10.mx/
3073
days inactive
3085
days old
12 comments
9 participants
participants (9)
-
bfranchuk＠jetnet.ab.ca -
cube1＠charter.net -
d235j.1＠gmail.com -
elson＠pico-systems.com -
mouse＠Rodents-Montreal.ORG -
tingox＠gmail.com -
toby＠telegraphics.com.au -
tor＠spacetec.no -
wmaddox＠pacbell.net