19 Oct
1999
19 Oct
'99
5:40 p.m.
I know its off-topic but i figured that since most of the poeple on this
list work or have worked on the really big stuff you'd know better than
most others.
Say someone were to home-build a CPU from scratch using only individual
components, no ICs only modern descrete(?) components. How big would the
CPU be? For comparison lets say it would be an 8080 clone. Any guesses?
pbboy
19 Oct
19 Oct
6 p.m.
Say someone were to home-build a CPU from scratch
using only individual
components, no ICs only modern descrete(?) components. How big would the
CPU be? For comparison lets say it would be an 8080 clone. Any guesses?
One of the vendors of bit-slice components (AMD 2900 or clone, I think)
offered a board that emulated an 8080. In addition to being faster than
an 8080, you could of course modify the microcode to add or change
instructions. IIRC, it looked like the board had about fifty chips.
If you didn't use a bit-slice, you'd have to use separate ALU, memory,
and shifter chips, and you'd wind up with even more.
The early microprocessor architectures were designed based on minimal
transistor count for a single-chip implementation. This does not result
in minimal chip count if you implement the equivalent in 7400-series
chips. It is quite possible to design useful processors with a lot fewer
TTL chips.
20 Oct
20 Oct
10:01 a.m.
Eric Smith wrote:
If you didn't use a bit-slice, you'd have to use separate ALU, memory,
and shifter chips, and you'd wind up with even more.
The early microprocessor architectures were designed based on minimal
transistor count for a single-chip implementation. This does not result
in minimal chip count if you implement the equivalent in 7400-series
chips. It is quite possible to design useful processors with a lot fewer
TTL chips.
FYI-> The 7400 series ALU-chip (4bit) is the 74181
Another way to go would be to use EPLD or a programmable ASIC chip. I
have heard stories of a Pr-Asic 486-clone "program" being aviable. Does
anyone know anything about this.
I've also been thinking about "cloning" a kinda 32bit clone of the
famous
TMS 9900. This chip had it's registers in memory and if such a design
would incorporate cache memory the results would still be respectable.
Especially if it could be done with programmable-asic technology.
Sipke de Wal
19 Oct
19 Oct
7:25 p.m.
I'd say about the size of a HP 9100. But it isn't a 8080 clone.
Joe
At 01:40 AM 10/20/99 -0400, you wrote:
I know its off-topic but i figured that since most of
the poeple on this
list work or have worked on the really big stuff you'd know better than
most others.
Say someone were to home-build a CPU from scratch using only individual
components, no ICs only modern descrete(?) components. How big would the
CPU be? For comparison lets say it would be an 8080 clone. Any guesses?
pbboy
20 Oct
20 Oct
8:27 a.m.
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1:36 a.m.
Say someone were to home-build a CPU from scratch
using only individual
components, no ICs only modern descrete(?) components. How big would the
CPU be? For comparison lets say it would be an 8080 clone. Any guesses?
ok, By discrete you meand transistors and diodes.
An 8080 cpu would likely fill a rack 20-25" high with boards.
The memory would have to be core for practicality as a static FF cell
uses lots of transistors and would be huge. using core 64k would likely
fill one or more 6" racks (using 1967ish technology). A uart would fill
a 9x11 board with TTL and that would expand to maybe 4-5 boards as
transistors/diodes.
A pdp-8 (early) had a pannel roughly 24"x50" with flip chip modules mostly
transistors and the 4k core was a 10" tall rack section. for rough
comparison. In many respects the 8080 is a far more complex CPU and would
be significantly bigger. It would also be slow compared to the NMOS part.
Doing it in ttl or bit slices would still be big, I've done that. using
2900 parts(ca mid to late '70s) the CPU equivelent was over 100 chips and
filled 4 10x8" cards.
Allison
3:27 a.m.
> Say someone were to home-build a CPU from scratch
using only individual
> components, no ICs only modern discrete(?) components. How big would the
> CPU be? For comparison lets say it would be an 8080 clone. Any guesses?
It seems to me the Right Answer is to approximate the number of transistors
required. How many transistors did an 8080 have? (Do remember, however,
that the transistor count is actually less than you'd need with discrete
transistors, because the on-chip transistors can have multpile emitters or
gates or whatever in the same device.)
As for how "big" it would be (that is, its size), modern discrete transistors
are available in tiny SOT-23 or even tinier packages. Resistors are
available in 0402 and maybe smaller. Line widths on PC boards can perhaps
be as small as .002 inches, and they can be many layers, a dozen or more.
So, in order to compute the size, I think you'd need to make two estimates:
1) The number of transistors per cubic inch (or cm if you like those units)
2) The number of transistors required.
This assumes some packaging/connector allowance is taken into account to
estimate the number of transistors per cubic whatever.
------
IMHO, if you're going to build something from transistors, why not build
something that was originally built with transistors? For example, the
IBM 1620, 1130, 1401, etc. Or if you really want to get funky, try something
like transistorizing a tube machine, like ENIAC or JOHNNIAC or Bendix G-15.
-That- could be entertaining...
-Mike Cheponis
3:28 a.m.
allisonp(a)world.std.com wrote:
[snip]
ok, By discrete you meand transistors and diodes.
An 8080 cpu would likely fill a rack 20-25" high with boards.
The memory would have to be core for practicality as a static FF cell
uses lots of transistors and would be huge. using core 64k would likely
fill one or more 6" racks (using 1967ish technology). A uart would fill
a 9x11 board with TTL and that would expand to maybe 4-5 boards as
transistors/diodes.
Using discrete transistors to build flop cells on that scale would be so
large that getting the timing to work would be a real pain. Core wouldn't be
bad at all; mid 70's core technology stuffed 32K * 20 in an 8" x 4"
area with no sweat; drivers and transceivers wouldn't double that.
I have trouble with the notion of the uart filling a 9 x 11 board given
that I'm holding one that's occupying 4 x 5 inches in SSI. Yeah, the shift
registers would take a bunch of space but I don't see it using anywhere
near the amount of real estate suggested.
In truth, since clock speed in such a beast is going to be low, dissipation
isn't going to be an overriding factor. The upper limit on flop density is
going to be how tightly we can physically pack the stuff, which is going to
be markedly higher than in the '60s. Discretes of similar functionality
are much smaller and we have routing tools which allow us to make use of
multilayer boards while our '60s compatriots were laying stuff out by hand
on light tables (been there, done that, never again).
A pdp-8 (early) had a pannel roughly 24"x50"
with flip chip modules mostly
transistors and the 4k core was a 10" tall rack section. for rough
comparison. In many respects the 8080 is a far more complex CPU and would
be significantly bigger. It would also be slow compared to the NMOS part.
I suspect you could build a pdp-8 using contemporary layout tools and discrete
technology that, excluding the core stack, was an order of magnitude smaller.
Using '70s core technology you could get the stack somewhat smaller while
increasing the storage density by a factor of eight. The 8080 would without
a doubt be larger than the '8 and slower than the NMOS version of the chip;
it would also cost a fortune to build.
Doing it in ttl or bit slices would still be big,
I've done that. using
2900 parts(ca mid to late '70s) the CPU equivelent was over 100 chips and
filled 4 10x8" cards.
That sounds about right; I recall building a PDP-11 clone using 2901/2910 parts
as part of an undergraduate CPU architecture course in the same era and using
about the same number of parts. Of course you can make most of the chip count
go away by tossing a single (small!) xilinx chip into the mix.
Best,
Chris
--
Chris Kennedy
chris(a)mainecoon.com
http://www.mainecoon.com
PGP fingerprint: 4E99 10B6 7253 B048 6685 6CBC 55E1 20A3 108D AB97
3:56 a.m.
Using discrete transistors to build flop cells on that
scale would be so
large that getting the timing to work would be a real pain. Core wouldn't be
bad at all; mid 70's core technology stuffed 32K * 20 in an 8" x 4"
area with no sweat; drivers and transceivers wouldn't double that.
Ok now delete all teh integrate circuits like the sense amps and substitue
a flipchip sized module for each read amp (note some of those chips were
duals and quads). Then look at the packages of diodes and use individual
diodes.
I have trouble with the notion of the uart filling a 9
x 11 board given
that I'm holding one that's occupying 4 x 5 inches in SSI. Yeah, the shift
registers would take a bunch of space but I don't see it using anywhere
near the amount of real estate suggested.
Try a TTY PDP-8 omibus card. Keeping in mind yes the uart part of that
is only part of the card it still has tobe interfaced. The ttl only
version is a full quad card. Again as transistors it will grow.
Having had my head in the RCSRI PDP-12 and LINC-8 plus the PB-250 I have a
better idea of real machines using nothing but transistor technology.
Granted modern parts could really improve the packing density.
multilayer boards while our '60s compatriots were
laying stuff out by hand
on light tables (been there, done that, never again).
Yes, touch way to go.
I suspect you could build a pdp-8 using contemporary
layout tools and discrete
technology that, excluding the core stack, was an order of magnitude smaller.
Using '70s core technology you could get the stack somewhat smaller while
increasing the storage density by a factor of eight. The 8080 would without
a doubt be larger than the '8 and slower than the NMOS version of the chip;
it would also cost a fortune to build.
Maybe. If you cheat and use 70s core tech (ICs) that's a big savings as
the core planes were never the total system anyway. It's the
drivers/decoders that grow huge!
Also you'll never get the power/cooling of a say straight-8 even if size
reduced to come down near as fast and the ultimate problem may be cooling
or deliver the AMPs of power.
Allison
4:36 a.m.
allisonp(a)world.std.com wrote:
My point is that using contemporary discretes I don't need a flip chip's
worth of real estate to implement a read or sense amp. The problem posed
was to build the thing using descretes, not discretes of 1960's vintage.
Equivalent power density and beta is available in packages sometime two
orders of magnitudes smaller -- although for core drivers the current
density would force things to be physically larger...
That's fair; the original statement that I responded to had to do with
the real estate used by the uart, not the uart and bus interface. Adding
in the bus interface for the 16 bit machine this is out of I'm looking
at about 50% more area. I'm not sure about the scaling to transistors;
this board is *anything* but dense; packages are on what looks like about
a one inch pitch. That's more than enough area to stuff the equivalent
discrete logic, assuming I use contemporary tools.
Funny, I found my box of rapidograph pens the other day...
I wasn't considering cheating. Decoding is strictly combinatorial, so that's not
tough. Driving and sense is much more of a bitch, and I probably can't get
away with surface mount devices because of the current density requirements.
Even so, I can build a similar function op amp using contemporary discretes in
a hell of a lot less space than using 60's technology -- just the reduction in
size of the passives gets me a hugh increase in density.
Using discrete transistors to build flop cells on
that scale would be so
large that getting the timing to work would be a real pain. Core wouldn't be
bad at all; mid 70's core technology stuffed 32K * 20 in an 8" x 4"
area with no sweat; drivers and transceivers wouldn't double that.
Ok now delete all teh integrate circuits like the sense amps and substitue
a flipchip sized module for each read amp (note some of those chips were
duals and quads). Then look at the packages of diodes and use individual
diodes. I have trouble with the notion of the uart
filling a 9 x 11 board given
that I'm holding one that's occupying 4 x 5 inches in SSI. Yeah, the shift
registers would take a bunch of space but I don't see it using anywhere
near the amount of real estate suggested.
Try a TTY PDP-8 omibus card. Keeping in mind yes the uart part of that
is only part of the card it still has tobe interfaced. The ttl only
version is a full quad card. Again as transistors it will grow. Having had my head in the RCSRI PDP-12 and LINC-8 plus
the PB-250 I have a
better idea of real machines using nothing but transistor technology.
Granted modern parts could really improve the packing density.
That's the point; aside from some high current applications (like core drivers)
I can get a tremendous increase in density by using autorouted multilayer
boards and SMD. If a 3' box fan positioned .5" from the board (quick, whose
70's
data sheet is that a reference to?) doesn't keep it cool we can always immerse
it in freon...
multilayer
boards while our '60s compatriots were laying stuff out by hand
on light tables (been there, done that, never again).
Yes, touch way to go. I suspect you could build a pdp-8 using
contemporary layout tools and discrete
technology that, excluding the core stack, was an order of magnitude smaller.
Using '70s core technology you could get the stack somewhat smaller while
increasing the storage density by a factor of eight. The 8080 would without
a doubt be larger than the '8 and slower than the NMOS version of the chip;
it would also cost a fortune to build.
Maybe. If you cheat and use 70s core tech (ICs) that's a big savings as
the core planes were never the total system anyway. It's the
drivers/decoders that grow huge! Also you'll never get the power/cooling of a say
straight-8 even if size
reduced to come down near as fast and the ultimate problem may be cooling
or deliver the AMPs of power.
Power distribution would be an issue, but it's certainly a tractable problem.
I've lost context on the dissapation/cooling issue. Certainly we'd burn less
and dissipate less (although more per square inch) than the original 8 did
if we built an 8 using contemporary discretes, and a discrete implementation of
an 8080 would run much hotter than the original 8.
Ugh. Back to working in the 90's.
Best,
Chris
--
Chris Kennedy
chris(a)mainecoon.com
http://www.mainecoon.com
PGP fingerprint: 4E99 10B6 7253 B048 6685 6CBC 55E1 20A3 108D AB97
6:21 a.m.
My point is that using contemporary discretes I
don't need a flip chip's
worth of real estate to implement a read or sense amp. The problem posed
was to build the thing using descretes, not discretes of 1960's vintage.
Equivalent power density and beta is available in packages sometime two
orders of magnitudes smaller -- although for core drivers the current
density would force things to be physically larger...
Then you bring that out to interconnect technology and it grows though
moden connectors are smaller/denser than the DEC blocks.
I can get a tremendous increase in density by using
autorouted multilayer
boards and SMD. If a 3' box fan positioned .5" from the board (quick, whose
70's
data sheet is that a reference to?) doesn't keep it cool we can always immerse
Signetics 82mumble WOM (write only memory) april first version.
I wasn't considering cheating. Decoding is
strictly combinatorial, so that's not
tough. Driving and sense is much more of a bitch, and I probably can't get
away with surface mount devices because of the current density requirements.
Even so, I can build a similar function op amp using contemporary discretes in
a hell of a lot less space than using 60's technology -- just the reduction in
size of the passives gets me a hugh increase in density.
The key here is mid 60s technology means to me a simple decoder like a
3 to 8 is now a lot of parts small or not. Sit down and think out a
"equivelnt of the 74138 decoder as trasistors, diodes and resistors.
Bet you end up with a lot of them.
I've lost context on the dissapation/cooling
issue. Certainly we'd burn less
and dissipate less (although more per square inch) than the original 8 did
if we built an 8 using contemporary discretes, and a discrete implementation of
an 8080 would run much hotter than the original 8.
Not much less. the disapation of the transistor was not size related but
the ability of a circuit to provide enough output for all the other loads.
Newer parts may have a higher beta, smaller size will have less
interconnect capacitance but we not in the order of magnitude department
here though it will be less. Newer devices would be smaller, faster,
and all but they are transistors and working at that level external
interconnect is very influential.
Allison
6:44 a.m.
allisonp(a)world.std.com wrote:
Yep. Suddenly this is starting to sound like something out of The Journal
or Irreproducable Results...
Oh, she's good. She's very good.
You're right, and I did. The number of components turns out to be fairly
ugly, although they can still be made to fit in a fairly small area --
although we'd need robotic assembly to place all the stuff -- and that's
assuming I didn't grossly screw up this design. Maybe I should spice it... ;-)
Absolutly no argument here. We play the same game in processor design
today; drive requirements (both due to fan out and L/C) make the
drivers bigger -- which drives up space, power and disapation requirements.
Mind games like this are fun at times; they remind us that, at least at times,
the more things change, the more they remain the same.
Best,
Chris
--
Chris Kennedy
chris(a)mainecoon.com
http://www.mainecoon.com
PGP fingerprint: 4E99 10B6 7253 B048 6685 6CBC 55E1 20A3 108D AB97
My point is that using contemporary discretes I
don't need a flip chip's
worth of real estate to implement a read or sense amp. The problem posed
was to build the thing using descretes, not discretes of 1960's vintage.
Equivalent power density and beta is available in packages sometime two
orders of magnitudes smaller -- although for core drivers the current
density would force things to be physically larger...
Then you bring that out to interconnect technology and it grows though
moden connectors are smaller/denser than the DEC blocks. I can get a tremendous increase in density by
using autorouted multilayer
boards and SMD. If a 3' box fan positioned .5" from the board (quick, whose
70's
data sheet is that a reference to?) doesn't keep it cool we can always immerse
Signetics 82mumble WOM (write only memory) april first version. I wasn't considering cheating. Decoding is
strictly combinatorial, so that's not
tough. Driving and sense is much more of a bitch, and I probably can't get
away with surface mount devices because of the current density requirements.
Even so, I can build a similar function op amp using contemporary discretes in
a hell of a lot less space than using 60's technology -- just the reduction in
size of the passives gets me a hugh increase in density.
The key here is mid 60s technology means to me a simple decoder like a
3 to 8 is now a lot of parts small or not. Sit down and think out a
"equivelnt of the 74138 decoder as trasistors, diodes and resistors.
Bet you end up with a lot of them. I've lost
context on the dissapation/cooling issue. Certainly we'd burn less
and dissipate less (although more per square inch) than the original 8 did
if we built an 8 using contemporary discretes, and a discrete implementation of
an 8080 would run much hotter than the original 8.
Not much less. the disapation of the transistor was not size related but
the ability of a circuit to provide enough output for all the other loads.
Newer parts may have a higher beta, smaller size will have less
interconnect capacitance but we not in the order of magnitude department
here though it will be less. Newer devices would be smaller, faster,
and all but they are transistors and working at that level external
interconnect is very influential.
8:47 a.m.
Signetics
82mumble WOM (write only memory) april first version.
Oh, she's good. She's very good. You're right, and I did. The number of components
turns out to be fairly
ugly, although they can still be made to fit in a fairly small area --
although we'd need robotic assembly to place all the stuff -- and that's
assuming I didn't grossly screw up this design. Maybe I should spice it... ;-)
;) designing with tubes or transistors is different and I'd bet if I
looked at the design I could trim out unneeded inversions or maybe by
adding an inverter use wired NOR logic instead of AND or NAND.
Mind games like this are fun at times; they remind us
that, at least at times,
the more things change, the more they remain the same.
That and it takes up back to the core electronics that makes it happen.
Myself I'd love to see three designs for a simple but useable if not
useful cpu one using MSI logic, one using SSI TTL and a simple buildable
transistor design (serial for simplicity).
In every case the memory can be modern or if something like serial
memory (drum, disk or delayline type) could be done with moden parts for
sanity sake.
Allison
10:48 a.m.
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11:52 a.m.
ard(a)p850ug1.demon.co.uk (Tony Duell) wrote:
Incidentally the nominal Vff is given as 6.3V. I wonder how many
modern-day engineers would realise the significance.
This is the point that zeners change from avalanche to
some other kind of break down that I can't remember
the name of. These made good noise generators.
Or, could you be talking about filiment voltages?
Dwight
3:40 p.m.
On Wed, 20 Oct 1999, Tony Duell wrote:
And old...
Memory says 82s129, I have the data sheet home in that 1971 signetics
data book. I was my first ttl databook!
The 82S129 was a fusible-link PROM. It was an actual device, and in
production until quite recently.
I have here the Signetics data sheet for the 25120 'Fully Encoded 9046*N
Random Access Write Only Memory'. I suspect that's the one you're
thinking of. It includes graphs of 'Bit Capacity .vs. temperature', 'Iff
.vs. Vff', 'Number of pins remaining .vs. Number of socket insertions'
and 'AQL .vs. Selling Price'... :-)
Incidentally the nominal Vff is given as 6.3V. I wonder how many
modern-day engineers would realise the significance.
Probably only those who had been exposed to transformer powered radios
and TVs. Suggests filament voltage to me.
- don
Signetics 82mumble WOM (write only memory) april first version.
Oh, she's good. She's very good. If anyone wants to get this data sheet, it's
reprinted on page 605 of the
'Student Manual for the Art of Electronics' by Thomas C Hayes and Paul
Horowitz (2nd Edition, ISBN 0-521-37709-9)
-tony
9:11 a.m.
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8:52 a.m.
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10:29 a.m.
Tony Duell wrote:
My memory is clearly failing with advancing age; that's the one, fabricated
using their proprietary process which was also known as "...A shovelful of
this to a shovelful of that..." :-)
I seem to recall a chip-destruct pin as well...
Best,
Chris
--
Chris Kennedy
chris(a)mainecoon.com
http://www.mainecoon.com
PGP fingerprint: 4E99 10B6 7253 B048 6685 6CBC 55E1 20A3 108D AB97
boards and SMD. If a 3' box fan positioned
.5" from the board (quick, whose 70's
data sheet is that a reference to?) doesn't keep it cool we can always immerse
it in freon...
A misquote of the Signetics WOM data sheet? At least the version I have
specifies a _6'_ fan 0.5" from the device. And then says something like
'If the device overheats, cooling was inadequate' :-)
11:43 a.m.
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10:15 a.m.
Allison wrote:
ok, By discrete you meand transistors and diodes.
An 8080 cpu would likely fill a rack 20-25" high with boards.
IIRC, the 8080 was about 4000 MOSFET transistors. If you implemented it
with individual FETs, and packed it densely, I think you could fit it in
a 10.5" high rack space easily, and a 5.25" high rack space with difficulty.
Of course, you'll need plenty of forced air cooling. From a serviceability
point of view, building it less densely is clearly better.
If you implemented it with bipolar transistors configured as saturating
logic, it would require perhaps twice as many transistors and a lot more
resistors for TTL logic, or 50% more transistors, a lot of diodes, and a
lot of resistors for DTL logic.
In many respects the 8080 is a far more complex CPU
and would
be significantly bigger. It would also be slow compared to the NMOS part.
Even in TTL-equivalent logic, it would be faster than the NMOS part if it
was designed reasonably well.
If you want blazing speed, build it with non-saturating logic like all the
early IBM 7000-series machines. That's equivalent to ECL. Now your
talking about a huge amount of power consumed and cooling needed.
2:27 p.m.
Hi,
I haven't been following this thread all that closely,
but the snippet below brought back some memories ...
Way back in '87 I visited the main Motorola facility in
Austin, TX. I was doing a lot of 68K-family based design
at that time for Nortel, and we were beginning to enter into a
strategic agreement with Motorola, so the folks there
were giving us a pretty in-depth tour of their facility.
I never will forget being taken into one of their
development labs, and over in a corner, on a shelf, were
two card cages. One was the prototype 68000 processor,
implemented on 11 wire-wrapped boards out of TTL logic
and similar-vintage components, all plugged into a
wire-wrapped backplane. Next to it was the prototype
68020 processor, which they were able to implement on 14
wire-wrapped boards. As I recall, these cards were a little
larger than what we were using in our systems at the time,
probably something like 12" x 12". I also recall them
telling me that the 68000 prototype ran the full instruction
set, and that it ran at a frequency of 500 KHz. I
hope that the folks at Motorola never threw that stuff out!
Regards,
Alex
Calculator History & Technology Museum Web Page
http://aknight.home.mindspring.com/calc.htm
At 10:15 PM 10/20/99 -0000, Eric Smith wrote:
Allison wrote:
...
ok, By discrete you meand transistors and
diodes.
An 8080 cpu would likely fill a rack 20-25" high with boards.
IIRC, the 8080 was about 4000 MOSFET transistors. If you implemented it
with individual FETs, and packed it densely, I think you could fit it in
a 10.5" high rack space easily, and a 5.25" high rack space with difficulty.
Of course, you'll need plenty of forced air cooling. From a serviceability
point of view, building it less densely is clearly better. 
22 Oct
22 Oct
12:36 a.m.
> ok, By discrete you meand transistors and
diodes.
> An 8080 cpu would likely fill a rack 20-25" high with boards.
IIRC, the 8080 was about 4000 MOSFET transistors.
Acording to Intels 'WebMuseum' they needed 6000 Transistors.
If you implemented it
with individual FETs, and packed it densely, I think you could fit it in
a 10.5" high rack space easily, and a 5.25" high rack space with difficulty.
Of course, you'll need plenty of forced air cooling. From a serviceability
point of view, building it less densely is clearly better.
Well, My own calculation comes also close around 25" hight.
Gruss
H.
--
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HRK
20 Oct
20 Oct
3:47 a.m.
I know its off-topic but i figured that since most of
the poeple on this
list work or have worked on the really big stuff you'd know better than
most others.
Well, I can't deny this...
Say someone were to home-build a CPU from scratch
using only individual
components, no ICs only modern descrete(?) components. How big would the
CPU be? For comparison lets say it would be an 8080 clone. Any guesses?
According to the intel Web site an 8080 has about 6000 Transistors.
Now, it is possible to put up some 12 to 16 FF gates in discrete
logic (discrete non SMD transistors etc.) gates (~40 Transistors)
onto one Euro-Card board (I tid once build up 16 FFs on one board
- at the age of 16, I tried to miniaturize :). So, spreading 6000
transistors at 40 transistors per board gives some 150 boards.
And with an asumption of 20 boards per row we need some 8 rows,
or a small (half height) rack.
As usual YMMV - especialy if you may change the design. And/or
build individual boards to maximize the number of transistors
per board (and of course try to replace as many as posible by
other circuits with less components).
For the 6502, the numbers are similar. I don't have a transistor
count, but a standard SC02 design consists of roughly 3,300 Gates,
adding up to a number like again 6-7,000 Transistors (BTW, the
65sc02 as PLD needs ~2.1k Altera Logic Cells, or ~1k of xilinx
LOgic Blocks).
Gruss
H.
P.S.: I scored an unused 8008 Processor last week - among a bunch
of other late 70s/early 80s chips...
--
Der Kopf ist auch nur ein Auswuchs wie der kleine Zeh.
H.Achternbusch
3:46 a.m.
According to the intel Web site an 8080 has about 6000
Transistors.
Now, it is possible to put up some 12 to 16 FF gates in discrete
logic (discrete non SMD transistors etc.) gates (~40 Transistors)
onto one Euro-Card board (I tid once build up 16 FFs on one board
- at the age of 16, I tried to miniaturize :). So, spreading 6000
transistors at 40 transistors per board gives some 150 boards.
And with an asumption of 20 boards per row we need some 8 rows,
or a small (half height) rack.
With gating and interconnect it will grow.! Also that would be a CPU chip
replacement... memory, IO and control pannel would be needed.
I think the key is yes it can be done. Yes with moden discretes and
technology you can compress it. However the devil is heat and a SMD
transisor at 10mW per is going to get hot with 40 per board! Why 10mW?
You have to drive wires and other gates and these are not MOS devices like
on the chip (you can but you still used real resistors) so things like
fanout/fanin are considerations.
While there are small serial computers a look at them shows some things
that need to be reflected upon. They were serial archetectures and
minimized the used of things like registers as they were hardware
intensive. The Minuteman Missle computer I"d played with many eons ago
was such an example. Flipflops were very scarce in that machine.
Allison
5:19 a.m.
> According to the intel Web site an 8080 has about
6000 Transistors.
> Now, it is possible to put up some 12 to 16 FF gates in discrete
> logic (discrete non SMD transistors etc.) gates (~40 Transistors)
> onto one Euro-Card board (I tid once build up 16 FFs on one board
> - at the age of 16, I tried to miniaturize :). So, spreading 6000
> transistors at 40 transistors per board gives some 150 boards.
> And with an asumption of 20 boards per row we need some 8 rows,
> or a small (half height) rack.
With gating and interconnect it will grow.! Also that
would be a CPU chip
replacement... memory, IO and control pannel would be needed.
Well, the whole question was about a CPU chip replacement,
_not_ a working computer including maybe 64K of Mem.
I think the key is yes it can be done. Yes with moden
discretes and
technology you can compress it. However the devil is heat and a SMD
transisor at 10mW per is going to get hot with 40 per board! Why 10mW?
You have to drive wires and other gates and these are not MOS devices like
on the chip (you can but you still used real resistors) so things like
fanout/fanin are considerations.
Well, I assumed _non_SMD - 10 mW per transistor isn't a wrong
asumption - also you should add some 50% more heat dispendes
by the needed resistors. So .6W per board sounds right - but
thats stil no big hassle. Using a proper rack, even 10W per
card can be handled without problems (with good airflow of
course).
While there are small serial computers a look at them
shows some things
that need to be reflected upon. They were serial archetectures and
minimized the used of things like registers as they were hardware
intensive. The Minuteman Missle computer I"d played with many eons ago
was such an example. Flipflops were very scarce in that machine.
Jep, but using a way different architecture than the original
CPU would again miss the design goal (at least in my opinion).
In fact, I've meditated over a similar question several times:
Wouldn't it be great to have 3 C64 at display (in a museum) with
3 different incarnations of a 6502(6510) - one with the 'real'
chip, one with a TTL replacement on lets say one board (like
Dicks wire wrap) and the third utilizeing a big box with transistors.
(And before y'all argue about backdraws, of course I know that
it is close to imposssible to get the TTL running at 1 MHz inside
the NMOS specs, but that can be solved by lowering the CPU clock
and selecting an aprobiate Application :)
I just belive this would give a _great_ display - unlike all
these dump displays where they put a sack of transistors beside
a uP and tell you just that they are equivalent.
Anyway
Gruss
H.
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Ich denke, also bin ich, also gut
HRK
5:10 a.m.
Well the 'straight 8' is about 2.5' tall, the PDP-5 is a bit taller but it
has its flip chips mounted vertically in the rack as opposed to back to back.
I don't doubt that you could fit an 8080 into a single 5' tall 19" rack.
--Chuck
At 01:40 AM 10/20/99 -0400, you wrote:
Say someone were to home-build a CPU from scratch using
only individual
components, no ICs only modern descrete(?) components. How big would the
CPU be? For comparison lets say it would be an 8080 clone. Any guesses?
pbboy
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