15 Dec
2018
15 Dec
'18
9:32 p.m.
On Sat, Dec 15, 2018 at 6:15 PM Rod G8DGR via cctalk <cctalk at classiccmp.org>
wrote:
All very interesting.. 1201 alarm while I deal will
all of the information
Rod
1202 coming up...
I don't know specifically about the various memory types being bandied
about, but I do know that the destructive read behavior of core memory my
be required for some architectures; "load and clear" type instructions rely
on the suppressing the write-after-read cycle to make the instruction
atomic, allowing the implementation of data locking instructions. For some
architectures, it may be that any replacement memory would have to support
the suppression signal to work correctly.
-- Charles
16 Dec
16 Dec
10 p.m.
On 12/15/2018 09:32 PM, Charles Anthony via cctech wrote:
On Sat, Dec 15, 2018 at 6:15 PM Rod G8DGR via cctalk
<cctalk at classiccmp.org>
wrote:
That's all fairy land speculation and guessing.? The person that started
this is working with
a PDP-8E so the above does not apply.? the 8E and later had both DEC
made ram and third
parties did when 2102 were cheap enough about 78ish.??? Later it was
battery backed up
cmos.? For system with disk a rom based booter was enough as who cares
if the ram held
valid stuff.? As to realism, the cost of a core was high enough then if
it broke or worse now
if it breaks its out of sight.? Breakage back then was costly, not its
possibly unobtainium.
The for the most part with the covers on the only thing noted was binary
blisters from the
switches and the incessant loud fans.?? In the mean time the user was
interacting with a
TTY with its notable noises and if needing service a sometimes bad
attitude.? The fact that
CORE does a R-Rewrite or RMW cycle is both unseen without a scope and
had no impact while
running a file though PAL-III in all caps.
In the end, current generation CMOS ram is the easy out, battery is
small, cost is small,? and
produces much less of the heat that is killer to systems.?? The only
reason to do that is core
cost big if you can find it for your machine.? I can cost more if you
want to run an OS that
needs a fair amount of it.? AC as well as it can help heat the room and
also power as in
makes the meter spin.
So much lathering and speculation about what and how.? When the point is
totally missed.
Allison
All very interesting.. 1201 alarm while I deal
will all of the information
Rod
1202 coming up...
I don't know specifically about the various memory types being bandied
about, but I do know that the destructive read behavior of core memory my
be required for some architectures; "load and clear" type instructions rely
on the suppressing the write-after-read cycle to make the instruction
atomic, allowing the implementation of data locking instructions. For some
architectures, it may be that any replacement memory would have to support
the suppression signal to work correctly.
-- Charles 
10:07 p.m.
On 12/16/2018 8:00 PM, allison via cctech wrote:
In the end, current generation CMOS ram is the easy
out, battery is
small, cost is small,? and
produces much less of the heat that is killer to systems.?? The only
reason to do that is core
cost big if you can find it for your machine.? I can cost more if you
want to run an OS that
needs a fair amount of it.? AC as well as it can help heat the room and
also power as in
makes the meter spin.
So much lathering and speculation about what and how.? When the point is
totally missed.
Allison
What programs or operating sytems require non volatile core?
Did DEC have any BOOTSTRAP programs in prom for the 8?
A small prom and regular slow mos memory may be the solution.
Ben.
10:30 p.m.
I put? focal in it...I leave? focal in it...? then I turn on the power? it talks focal to?
a tty!
( for? grains? want? ?copy? of? focal? 11? for the 11/20? too...)
?
But? definitely? want to? see focal on a? little omnibus 8! Just like that famous night in
1979......
Life? is? good? ? Ed#
?
In a message dated 12/16/2018 8:08:01 PM US Mountain Standard Time, cctech at
classiccmp.org writes:
?
What programs or operating sytems require non volatile core?
Did DEC have any BOOTSTRAP programs in prom for the 8?
A small prom and regular slow mos memory may be the solution.
Ben.
10:49 p.m.
Sent from Mail for Windows 10
From: ben via cctech
Sent: 17 December 2018 03:08
To: cctech at classiccmp.org
Subject: Re: Core memory emulator using non volatile ram.
On 12/16/2018 8:00 PM, allison via cctech wrote:
In the end, current generation CMOS ram is the easy
out, battery is
small, cost is small,? and
produces much less of the heat that is killer to systems.?? The only
reason to do that is core
cost big if you can find it for your machine.? I can cost more if you
want to run an OS that
needs a fair amount of it.? AC as well as it can help heat the room and
also power as in
makes the meter spin.
So much lathering and speculation about what and how.? When the point is
totally missed.
Allison
What programs or operating sytems require non volatile core?
Did DEC have any BOOTSTRAP programs in prom for the 8?
A small prom and regular slow mos memory may be the solution.
Ben.
I?m trying to make a look and feel reproduction PDP-8/e.
So the memory characteristics need to be as close as possible.
An original ( and I do have one) and the copy when placed side by side should run in
sync.
When executing he same code ? What code I couldn?t care.
Rod
11:04 p.m.
On 12/16/2018 10:07 PM, ben via cctech wrote:
On 12/16/2018 8:00 PM, allison via cctech wrote:
None.
Non volitility was handy if you wanted to power down go home and restart
where you were
the next day but at the OS level that was never a consideration.
CMOS is MOS!? Current generation parts are cheap and easy to use.? Its
not a speed issue as
core was so slow, PDP-8 the fastest core was 1.5uS and even current cmos
(5101) was under 1uS.
No advanatage for slow memory as everything from 1978 on was likely much
faster than an 8e
needed anyway.?
The easy way if obvious use cmos as its cheap and common as house
flies.? Leave out the
small lithium cell.?
The problem is PROM cards for PDP-8 omnibus was not common at at then
then time cheap
and used parts likely to be unobtainium now.? The machines that had it
used an abbreviated
front panel? maybe 12 sense switches for the OSR instruction and a
boot/start switch.? Not many
made and FS contract required the full panel to do checkout and fix.? So
cost wise the boot card
was not common.? Call it an artifact of systems then.
The loader for most stuff was small anyway, toggle it in, usually rim or
bin loaders.? Run the reader
and that loaded whatever.
Typical small non disk systems were CPU, TTY and maybe a high speed
reader.? Next level added TU56
or maybe RX01 floppy, from there a DF32 disk and maybe a RK05 or two.?
The user interacted with them the box ala the CPU was a small part of
that interaction/experience.
Allison
In the end, current generation CMOS ram is the
easy out, battery is
small, cost is small,? and
produces much less of the heat that is killer to systems.?? The only
reason to do that is core
cost big if you can find it for your machine.? I can cost more if you
want to run an OS that
needs a fair amount of it.? AC as well as it can help heat the room and
also power as in
makes the meter spin.
So much lathering and speculation about what and how.? When the point is
totally missed.
Allison
What programs or operating sytems require non volatile core?
Did DEC have any BOOTSTRAP programs in prom for the 8?
A small prom and regular slow mos memory may be the solution.
Ben.
17 Dec
17 Dec
9:30 a.m.
On Dec 16, 2018, at 10:07 PM, ben via cctalk
<cctalk at classiccmp.org> wrote:
On 12/16/2018 8:00 PM, allison via cctech wrote:
Before boot ROMs, it was standard practice to toggle the boot loader into core where it
would be available indefinitely, including across power cycles. You can see this in the
PDP-8, and it was also documented in the early days of the PDP-11 (though in 1973 I
didn't have to do this, we had a 16-word diode matrix boot ROM).
RSTS-11 V4 had optional power fail handling, which would allow it to continue running
after a power cycle. Not by rebooting as later versions did, but by continuing from where
it left off. It would have to reinitialize the I/O devices since I/O registers are
volatile, but the OS in memory would be intact and logged in user sessions would be
preserved. I actually saw that work once, pretty neat.
For all this, the only necessary memory property is simply that the contents was preserved
across power cycles. None of the other details of core memory are important. For that
matter, core memory details such as destructive read weren't visible to the CPU; the
read/restore cycle was handled inside the core memory logic. That's typical; one
exception I know of is the CDC 6000 series peripheral processor, which I mentioned before:
there the restore cycle is part of the main execution pipeline. That's why readstart
(system reboot) drops a zero in memory, it disrupts that read/restore cycle.
paul
In the end, current generation CMOS ram is the
easy out, battery is
small, cost is small, and
produces much less of the heat that is killer to systems. The only
reason to do that is core
cost big if you can find it for your machine. I can cost more if you
want to run an OS that
needs a fair amount of it. AC as well as it can help heat the room and
also power as in
makes the meter spin.
So much lathering and speculation about what and how. When the point is
totally missed.
Allison
What programs or operating sytems require non volatile core?
Did DEC have any BOOTSTRAP programs in prom for the 8?
A small prom and regular slow mos memory may be the solution.
Ben.
2078
days inactive
2079
days old
6 comments
6 participants
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