Subject: Re: Re: T11 design WAS - Re: Inside old games machines, was: Re:,Simulated CP/M-68K? From: Johnny Billquist <bqt at softjar.se> Date: Sat, 23 Jun 2007 02:43:26 +0100 To: cctalk at classiccmp.org Allison <ajp166 at bellatlantic.net> skrev: Re: Simulated CP/M-68K? <cctalk at classiccmp.org> No, it isn't. Where did you get that? (And I've just triple checked my memory by actually reading through parts of the 11/40 and 11/70 manuals.) The 11/70 don't even have a read-modify-write cycle defined on the memory bus. If you write less than 32 bits, the memory box itself must do the read-modify-write cycle. The CPU and memory bus is totally unaware of that detail. On the Unibus, the processor can use both pure write cycles (DATO/B) or read-modify-write (DATIP followed by DATO/B).

The memory systems can, and must be able to deal with both. Saying that RMW is a part of the memory to memory design is pure nonsense. And the same for how instructions work. It depends on wether the instruction mandates that it's a RMW or not. Arithmentic instructions for instance, are typical read-modify-write, while pure writes becomes pure writes on the bus to memory as well.

So in short: writes on PDP-11 systems in general don't imply a read. That's a T-11 thing if it does, and is probably related to simplifying the design (internal) more than anything else. I don't think they did it with core memories in mind. All Unibus core memories have their own write-back. That isn't something the CPU bothers with. For the Q-bus, I don't even know if any core memories exist.

Johnny