Date: Mon, 2 Jul 2012 20:11:01 -0400 From: Michael Thompson <michael.99.thompson at gmail.com> To: cctech <cctech at classiccmp.org> Subject: Strange Core Memory Behavior in a PDP-8/L Message-ID: <CAH1BU=9z5sOj5rw0dzb1hPe4PTrMvYpjiOv2dPRnrXJ-5CuqwA at mail.gmail.com> Content-Type: text/plain; charset=ISO-8859-1 The RICM is still wrestling with the core in the PDP-8. After replacing some diodes on the core stack we have all addresses working. We observed an interesting core memory behavior during our debugging last Saturday. We started the memory alignment procedure by looking at the STROBE FIELD 0 signal and the amplifier output on pin E1 of the sense amplifier. The STROBE signal was very late compared to Figure 5-6 in the 8/L Maintenance Manual. We ran a short JMP loop and adjusted the relationship with the trimpot on the M360 delay module. When we halted the processor and tried a examine core we only got just zeros. We adjusted the M360 delay back where it was and single step worked again. We found that the strobe-to-one-bit relationship was almost 100ns earlier when in single-step than it was with the processor running. We checked the whole timing path from MEM START at pin N2 of the M113 in slot C03, through all of the gates, delays, and flip-flops, and found no timing difference between single-step and running. Right now it looks like there is a 100ns delay difference between the READ(1) signal that turns on the current in the core and the bit signal showing up on the E1 pin of the sense amplifier when in the single-step and running. Is this normal behavior? The first thing that comes to mind is one-shot recovery time. I might guess that some component has degraded, and the one-shot has a different delay when it has been recently triggered vs. when it has sat for a while. (I'm assuming a classic 8, with discrete transistors, not a later machine built with ICs.) Most specifically, there probably is a transistor that resets the capacitor at the end of the one-shot cycle, and if that transistor is weak, it may not get the cap fully discharged before the next memory cycle starts. Most core memories had circuits to adjust drive current based on core plane temperature, maybe some adjusted timings as well. Also, check for dead decoupling capacitors, these could allow noise when running to alter timings. Jon