14 Nov
2017
14 Nov
'17
3:20 p.m.
Having picked up one of these little TI Compact Computer-40 (cc40) units
over the Summer, I thought I'd work on reverse engineering a RAM
cartridge for the unit.
As shown on this forum:
http://atariage.com/forums/topic/255728-the-compact-computer-40-cc40/?p=389…
The design *appears* to havea? "floating" ground when powered off
battery alone.? The cartrridge edge connector has 2 grounds.? I didn't
think anything about them at first, assuming they were connected to each
other.
Hwoever, someone with a RAM cart is helping me reverse engineer, and it
appears pin 1 ground is connected to the RAM GND pin, but is connected
via a 6K8 resistor to the 3V battery ground, which is connected to pin
27 ground line.
I *assume* this means that, once the cart is pulled, the battery voltage
sits somewhere in the middle of the 5V swing the RAM needs to see, but I
can;t figure out how one calculates the voltage divider value for the
inherent resistance of an SRAM, as the 3V is sent through a germanium
diode (bringing the effective Vcc of the SRAM to 2.7V), and then SRAM
ground is sent through the 6K8 to battery ground.
Obviously, reverse engineering being fraught with errors, we could be
wrong, but assuming not, what is going on in this circuit, and how does
one calculate the effective potential of the GND pin of the SRAM?
Pics:
http://www.go4retro.com/downloads/CC40RAM/
Jim
--
Jim Brain
brain at jbrain.com
www.jbrain.com
14 Nov
14 Nov
4:32 p.m.
On 2017-Nov-14, at 3:20 PM, Jim Brain via cctalk wrote:
Having picked up one of these little TI Compact
Computer-40 (cc40) units over the Summer, I thought I'd work on reverse engineering a
RAM cartridge for the unit.
As shown on this forum:
http://atariage.com/forums/topic/255728-the-compact-computer-40-cc40/?p=389…
The design *appears* to havea "floating" ground when powered off battery
alone. The cartrridge edge connector has 2 grounds. I didn't think anything about
them at first, assuming they were connected to each other.
Hwoever, someone with a RAM cart is helping me reverse engineer, and it appears pin 1
ground is connected to the RAM GND pin, but is connected via a 6K8 resistor to the 3V
battery ground, which is connected to pin 27 ground line.
I *assume* this means that, once the cart is pulled, the battery voltage sits somewhere
in the middle of the 5V swing the RAM needs to see, but I can;t figure out how one
calculates the voltage divider value for the inherent resistance of an SRAM, as the 3V is
sent through a germanium diode (bringing the effective Vcc of the SRAM to 2.7V), and then
SRAM ground is sent through the 6K8 to battery ground.
Obviously, reverse engineering being fraught with errors, we could be wrong, but assuming
not, what is going on in this circuit, and how does one calculate the effective potential
of the GND pin of the SRAM?
Pics:
http://www.go4retro.com/downloads/CC40RAM/
Once the cart is pulled the 4008 chip should end up in standby mode - no enables
asserted.
In standby a CMOS chip like this will appear as a near infinite impedance, so there
isn't much voltage dividing going on with a 6.8K R.
The full battery voltage (minus epsilon) will be across the chip.
The datasheet specs standby current Isb1 at typically 4 uA (50 max).
Ohm's law will get you an idea of the effective resistance of the chip if you really
want to calculate what epsilon is here.
CMOS memory doesn't require current to hold it's state, just the voltage
potential.
Kind of like a tire holding it's shape just with air pressure (potential differential
to the outside air), it doesn't require air flow or power to hold up.
As with the tire however, there is leakage, which is what would constitute Isb1.
From my own measurements with some CMOS chip holding
config in some equipment, Vcc can typically drop pretty low in standby and still hold
state.
Why the circuit might be as you have it with the 6.8K I'm not sure, perhaps for some
current limiting or glitch suppression as the cart is pulled out/in.
Doesn't really matter much as the only other thing on that gnd side is the switches.
Those 4 10K resistors are kind of weird, each 'on' switch is chewing up orders of
magnitude more battery current than the chip,
might make more sense if they went to Vcc where they would be diode blocked when the cart
is on battery.
4:51 p.m.
On 11/14/2017 6:32 PM, Brent Hilpert via cctalk wrote:
Once the cart is pulled the 4008 chip should end up in standby mode - no enables
asserted.
The 3K3 ties both !CROM and !CRAM high, and they are both open collector
outputs on the port.
But, I forgot to put one important detail in the original note.? I so
apologize.? The original cart has a HM62256LP-12, but it is evident from
the traces being cut on the cart that this was not even the original
SRAM.? I do believe the original SRAM was 32kB in size, though.
SInce the original SRAM was not even original, I replaced with the '4008
for various reasons.
In standby a CMOS chip like this will appear as a near infinite impedance, so there
isn't much voltage dividing going on with a 6.8K R.
The full battery voltage (minus epsilon) will be across the chip.
Then, why do the
6K8 there?
The datasheet specs standby current Isb1 at typically 4 uA (50 max).
Ohm's law will get you an idea of the effective resistance of the chip if you really
want to calculate what epsilon is here.
I'll try and calculate it for the
HM62256LP, which seems to be .5mA
under no load:
http://www.farnell.com/datasheets/97905.pdf
(2.7/.0005) = 5K4???? That seems incomplete, like I need to also take
into account that .5mA flows through the 6800 resistor, but that means
(6800*.0005) = 3.4V, which can't be right.
If I put that into a Voltage Divider (2.7V Vih, R1 = 5400, R2 = 6800,
output is 1.5V, implying the GND line is at 1.5V relative to the battery...
Why the circuit might be as you have it with the 6.8K I'm not sure, perhaps for some
current limiting or glitch suppression as the cart is pulled out/in.
Doesn't really matter much as the only other thing on that gnd side is the switches.
And they aren't there on the original.
Those 4 10K resistors are kind of weird, each 'on' switch is chewing up orders of
magnitude more battery current than the chip,
Good point.? I copied the design from
the "ROM cart" schematic, where
the battery is not in place, and the switches were there to choose the
bank of 32K that would be visible in the address space. I should
reconsider the schematic, and...
might make more sense if they went to Vcc where they
would be diode blocked when the cart is on battery.
Excellent suggestion.? I will do so.
--
Jim Brain
brain at jbrain.com
www.jbrain.com
6:29 p.m.
On 2017-Nov-14, at 4:51 PM, Jim Brain via cctalk wrote:
On 11/14/2017 6:32 PM, Brent Hilpert via cctalk
wrote:
With the 62256 drawing consequential standby current, you can't ensure an accurate
calculated value for
the voltage division from specs as the chip current probably isn't a linear relation
to Vcc.
But going from what we have:
Isb @ 5V Vcc = 0.5ma then chip R = 5V / 0.0005A = 10 Kohms
2.7V Vbatt * 10000 / (10000+6800) = 1.6V across the chip supply pins.
But from the datasheet it also looks like Isb goes down considerably (40uA) if the voltage
on nCS approaches Vcc
and other inputs pins go to 0V, as it might/would/should with the cart pulled.
That would be a higher effective R for the chip and so a higher V supply for the chip.
There is another potential problem with those switches though,
it's not clear to me whether you resolved whether X1P pins 1 & 27 connect together
when plugged into the computer.
If not, then when plugged in and operational, the switch 10K Rs form a varying voltage
divider with the 6.8K and the
input levels on bank-select address pins would be all over the place.
I would suggest you redraw the schematic with GND as the chip/computer GND
rather than establishing a second GND, and have a bus line across the bottom for the
battery negative.
If you move the switches R supply it may be a good idea to put another diode in series to
give a similar V drop as the main supply diode
so the V on the bank address pins doesn't go above the chip Vcc.
I'm not clear on what all is going on there between original design and modifications
and additions.
Once the cart is pulled the 4008 chip should end up in standby mode - no enables
asserted.
The 3K3 ties both !CROM and !CRAM high, and they are both open collector
outputs on the port.
But, I forgot to put one important detail in the original note. I so apologize. The
original cart has a HM62256LP-12, but it is evident from the traces being cut on the cart
that this was not even the original SRAM. I do believe the original SRAM was 32kB in
size, though.
SInce the original SRAM was not even original, I replaced with the '4008 for various
reasons.
In standby a CMOS chip like this will appear as a near infinite impedance, so there
isn't much voltage dividing going on with a 6.8K R.
The full battery voltage (minus epsilon) will be across the chip.
Then, why do the
6K8 there?
The datasheet specs standby current Isb1 at typically 4 uA (50 max).
Ohm's law will get you an idea of the effective resistance of the chip if you really
want to calculate what epsilon is here.
I'll try and calculate it for the
HM62256LP, which seems to be .5mA under no load:
http://www.farnell.com/datasheets/97905.pdf
(2.7/.0005) = 5K4? That seems incomplete, like I need to also take into account that
.5mA flows through the 6800 resistor, but that means (6800*.0005) = 3.4V, which can't
be right.
If I put that into a Voltage Divider (2.7V Vih, R1 = 5400, R2 = 6800, output is 1.5V,
implying the GND line is at 1.5V relative to the battery...
Why the circuit might be as you have it with the 6.8K I'm not sure, perhaps for some
current limiting or glitch suppression as the cart is pulled out/in.
Doesn't really matter much as the only other thing on that gnd side is the switches.
And they aren't there on the original.
Those 4 10K resistors are kind of weird, each 'on' switch is chewing up orders of
magnitude more battery current than the chip,
Good point. I copied the design from
the "ROM cart" schematic, where the battery is not in place, and the switches
were there to choose the bank of 32K that would be visible in the address space. I should
reconsider the schematic, and...
might make more sense if they went to Vcc where
they would be diode blocked when the cart is on battery.
Excellent suggestion. I will do so. 
15 Nov
15 Nov
7:11 a.m.
Why not just measure the voltage across the resistor. That will tell you the amount of
current flowing.
Dwight
________________________________
From: cctalk <cctalk-bounces at classiccmp.org> on behalf of Brent Hilpert via
cctalk <cctalk at classiccmp.org>
Sent: Tuesday, November 14, 2017 6:29:47 PM
To: General Discussion: On-Topic and Off-Topic Posts
Subject: Re: Need help with an odd design construct
On 2017-Nov-14, at 4:51 PM, Jim Brain via cctalk wrote:
On 11/14/2017 6:32 PM, Brent Hilpert via cctalk
wrote:
With the 62256 drawing consequential standby current, you can't ensure an accurate
calculated value for
the voltage division from specs as the chip current probably isn't a linear relation
to Vcc.
But going from what we have:
Isb @ 5V Vcc = 0.5ma then chip R = 5V / 0.0005A = 10 Kohms
2.7V Vbatt * 10000 / (10000+6800) = 1.6V across the chip supply pins.
But from the datasheet it also looks like Isb goes down considerably (40uA) if the voltage
on nCS approaches Vcc
and other inputs pins go to 0V, as it might/would/should with the cart pulled.
That would be a higher effective R for the chip and so a higher V supply for the chip.
There is another potential problem with those switches though,
it's not clear to me whether you resolved whether X1P pins 1 & 27 connect together
when plugged into the computer.
If not, then when plugged in and operational, the switch 10K Rs form a varying voltage
divider with the 6.8K and the
input levels on bank-select address pins would be all over the place.
I would suggest you redraw the schematic with GND as the chip/computer GND
rather than establishing a second GND, and have a bus line across the bottom for the
battery negative.
If you move the switches R supply it may be a good idea to put another diode in series to
give a similar V drop as the main supply diode
so the V on the bank address pins doesn't go above the chip Vcc.
I'm not clear on what all is going on there between original design and modifications
and additions.
Once the cart is pulled the 4008 chip should end up in standby mode - no enables
asserted.
The 3K3 ties both !CROM and !CRAM high, and they are both open collector
outputs on the port.
But, I forgot to put one important detail in the original note. I so apologize. The
original cart has a HM62256LP-12, but it is evident from the traces being cut on the cart
that this was not even the original SRAM. I do believe the original SRAM was 32kB in
size, though.
SInce the original SRAM was not even original, I replaced with the '4008 for various
reasons.
In standby a CMOS chip like this will appear as a near infinite impedance, so there
isn't much voltage dividing going on with a 6.8K R.
The full battery voltage (minus epsilon) will be across the chip.
Then, why do the
6K8 there?
The datasheet specs standby current Isb1 at typically 4 uA (50 max).
Ohm's law will get you an idea of the effective resistance of the chip if you really
want to calculate what epsilon is here.
I'll try and calculate it for the
HM62256LP, which seems to be .5mA under no load:
http://www.farnell.com/datasheets/97905.pdf
(2.7/.0005) = 5K4? That seems incomplete, like I need to also take into account that
.5mA flows through the 6800 resistor, but that means (6800*.0005) = 3.4V, which can't
be right.
If I put that into a Voltage Divider (2.7V Vih, R1 = 5400, R2 = 6800, output is 1.5V,
implying the GND line is at 1.5V relative to the battery...
Why the circuit might be as you have it with the 6.8K I'm not sure, perhaps for some
current limiting or glitch suppression as the cart is pulled out/in.
Doesn't really matter much as the only other thing on that gnd side is the switches.
And they aren't there on the original.
Those 4 10K resistors are kind of weird, each 'on' switch is chewing up orders of
magnitude more battery current than the chip,
Good point. I copied the design from
the "ROM cart" schematic, where the battery is not in place, and the switches
were there to choose the bank of 32K that would be visible in the address space. I should
reconsider the schematic, and...
might make more sense if they went to Vcc where
they would be diode blocked when the cart is on battery.
Excellent suggestion. I will do so.
2378
days inactive
2379
days old
4 comments
3 participants
participants (3)
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bhilpert＠shaw.ca -
brain＠jbrain.com -
dkelvey＠hotmail.com