QBUS VAX and M7941 under VMS - info needed! - test-drb@ccmp.vtda.org

18 Apr 2002

...
  Date: Thu, 18 Apr 2002 17:45:50 -0700
 From: cdl(a)proxima.ucsd.edu (Carl Lowenstein)
 To: classiccmp(a)classiccmp.org
 Subject: Re: QBUS VAX and M7941 under VMS - info needed!
 It's sort of standard DEC for a parallel interface.
 CSR + 2 is the output buffer, connected to connector J1
        Bits in CSR+2 are read/write to the CPU
 CSR + 4 is the input buffer, connected to connector J2
        Bits in CSR+4 are read-only to the CPU
 CSR has the usual INT_ENB A at <6> and INT_ENB A at <5>
 INT_ENB AND REQ makes an interrupt.  Interrupt A at VEC, B at VEC+4.
 Information from "microcomputer interfaces handbook 1980"
 EB-17723-20 
Add-on to my own post.  While driving home I remembered something
that has bothered me about DEC parallel interfaces (DR11, DRV11)
for nearly 30 years.  Why couldn't they make the programming model
the same as the single-channel serial interface?
Input control   CSR
Input data      CSR+2
Output control  CSR+4
Output data     CSR+6
Then you could use the same software driver for an 8-bit parallel device
or an 8-bit serial device.  Just plug in a different bit of hardware.
Actually the Heathkit 16-bit parallel Qbus card was like that.
    carl
--
        carl lowenstein   marine physical lab   u.c. san diego
                                          clowenstein(a)ucsd.edu