I'm not enough of a PA-RISC conniseur to claim that there's nothing like microcode In there but... PA-RISC was a very consciously RISC effort. Shift-and-add instructions are part of the PA-RISC instruction set. Deragatory remarks from CISCy folks complained that PA-RISC instructions were in fact microcode :-). Some block diagrams are in the CE handbook at http://bitsavers.org/pdf/hp/9000_800/ According to openpa.net, they did a lot of good stuff with just 150 chips. I contrast with other minis of the 70's and early 80's which did much less with many more chips. From openpa.net: The TS-1 was the first PA-RISC production processor, introduced in 1986. It integrated version 1.0 of PA-RISC on six boards (each 8.4?11.3?) of TTL. Details: PA-RISC version 1.0 32-bit Three-stage pipeline The CPU consists of six separate boards: I-unit: the Instruction Unit Register File Board, contains general and control registers E-unit: the Execution Unit TLB, the translation lookaside buffer with 4096 entries for 2?KB pages Cache controller with split instruction and data caches ? 64?KB for each I and D FPC, the floating-point coprocessor, handles FP operations parallel to the CPU/ALU (the ADD/MUL/DIV chip was taken over from the HP 9000/550 FOCUS system) 4096-entry TLB off-chip, direct-mapped Off-chip L1 cache of 128?KB (I/D) direct-mapped/one-way associative Physical address space of 27-bit (128?MB main memory could be addressed) 8?MHz clock speed Six (some sources say five) printed circuit boards, implemented in FAST TTL and (25ns and 35ns) SRAMs/PALs, which each about 150 ICs Tim.