22 Oct
2016
22 Oct
'16
12:44 p.m.
Hello Dave,
exactly!
But in place of a plain FPGA, nowadays I would choose a FPGA-ARM board,
for example
the ZedBoard MicroZed or the Myirtech Z-turn, both of them have a Zynq
onboard,
and they can run linux for the software side and programmable logic for
the interface side.
Very nice and flexible.
For the development, I'm trying to figure if an hybrid QBUS / UNIBUS
solution is possible.
Of course one have to switch some jumper to avoid conflicts, but hey, in
the end you
would have a true universal board.
What kind of bus transceivers did you used for the QSIC, specially
because you have
to go from 5V open-drain logic to 3.3V logic?
Thanks
Andrea
On 10/21/2016 07:00 PM, cctalk-request at classiccmp.org wrote:
You mean, perhaps, something like this?
http://pdp10.froghouse.org/qsic/html/overview.html
22 Oct
22 Oct
6:40 p.m.
New subject: DEC bus transceivers (was Re: Unibus disk controller with modern storage)
On 10/22/2016 12:44 PM, shadoooo wrote:
What kind of bus transceivers did you used for the
QSIC, specially
because you have
to go from 5V open-drain logic to 3.3V logic?
To add to Noel's answer, here's a picture of our current prototype board.
http://pdp10.froghouse.org/qsic/qsic-wirewrap.jpg
Coming up from the QBUS, the first two rows of chips are the bus
transceivers. The next row and a half are the level-converters. Then
the two large ribbon cables run off to the FPGA module we're using for
development. The two small ribbon cables go to the indicator panel.
Just the bus interface takes over half the area of a dual-height board!
I've played around with laying out what might be the production board
(when I get tired of Verilog and want a mindless break, I doodle with
kicad) and I've got it down to a row of 8641 bus transceivers and a row
or two of the level-converter chips. It's better but still a good
fraction of the entire board.
http://pdp10.froghouse.org/qsic/proto-pcb.jpg
Now I thought, what if my idea of that two MOSFET bus transceiver would
work? What would the board look like then?
http://pdp10.froghouse.org/qsic/qsic-smt.jpg
Obviously that could be squeezed down a lot more. Even another
transistor or two per bus line would still be fairly small. Doing the
bus transceiver and level-conversion in one step makes a big difference.
For the QSIC, we're going to have sufficient room and we're able to find
enough old bus transceivers to continue on as we're going. Still, I'd
sure love to have an option that used production parts and took up less
board space.
7:52 p.m.
New subject: DEC bus transceivers (was Re: Unibus disk controller with modern storage)
On 10/22/2016 06:40 PM, David Bridgham wrote:
On 10/22/2016 12:44 PM, shadoooo wrote:
For bus to card LS241, LS244 and LS245 were used in the day by heathkit
(H11)
For bus to card with hysteresis LS14 was a common choice along with
LS13 or maybe LS132.
Other considerations the DEC specs were based on available devices of
the day (late 70s)
and in the last 40 years there are a plethora of better devices that
replace those easily.
The key being Schmidt input (bus to card level) for noise immunity and
robust drive for the
output devices. Many of those were also used for S100 (less well
thought out and
often noisier.) with good success. I've copied and used those for
making boards as
needed for Qbus and Omnibus as those represent the common DEC buses
outside of SCSI
in the hardware I own.
One thing I'm adverse to is bus to CMOS without buffering or the reverse
even if
the CMOS can drive the bus. Unexpected ringing or spikes on the bus can
play
havoc with those as well as poor ESD practices.
Now the problems of board space and available parts may force SMT and CMOS
for the internal circuits and also power conservation (and thermal
management).
Allison
What kind of bus transceivers did you used for
the QSIC, specially
because you have
to go from 5V open-drain logic to 3.3V logic?
To add to Noel's answer,
here's a picture of our current prototype board.
http://pdp10.froghouse.org/qsic/qsic-wirewrap.jpg
Coming up from the QBUS, the first two rows of chips are the bus
transceivers. The next row and a half are the level-converters. Then
the two large ribbon cables run off to the FPGA module we're using for
development. The two small ribbon cables go to the indicator panel.
Just the bus interface takes over half the area of a dual-height board!
I've played around with laying out what might be the production board
(when I get tired of Verilog and want a mindless break, I doodle with
kicad) and I've got it down to a row of 8641 bus transceivers and a row
or two of the level-converter chips. It's better but still a good
fraction of the entire board.
http://pdp10.froghouse.org/qsic/proto-pcb.jpg
Now I thought, what if my idea of that two MOSFET bus transceiver would
work? What would the board look like then?
http://pdp10.froghouse.org/qsic/qsic-smt.jpg
Obviously that could be squeezed down a lot more. Even another
transistor or two per bus line would still be fairly small. Doing the
bus transceiver and level-conversion in one step makes a big difference.
For the QSIC, we're going to have sufficient room and we're able to find
enough old bus transceivers to continue on as we're going. Still, I'd
sure love to have an option that used production parts and took up less
board space.
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