PDP 11/24 - A Step Backwards - test-drb@ccmp.vtda.org

29 Mar 2022

...
  From: Brent Hilpert 
...
  But the LED and CPU clock are not driven directly by
that RC oscillator
 - there's a bunch of logic in-between the oscillator and the LED / CPU
 clock. 
Oh, sure; it was late (for me; the dog woke me up at AM today :-), and it had
taken me a while to get even that far (find the freakin' thing), so I just
wanted to pass the ball forward and crash!

I saw the "STOP OSC H" signal feeding into the production of "PRE OSC
L", but
couldn't fully work out all the things that fed into that - and it now looks
like that's not an important thing anyway, "MCLK H" is the one to look at.

...
  [RC clock] => K1 OSC H/L
	--> [4-bit counter w parallel load] => K1 MCLK H/L
		--> LED 
It seems to me that the LED, being driven directly by MCLK L, should be
flashing at the basic clock rate (i.e. dim to the eye) - so if it's totally
off, MCLK L must not be running. So that's thing absolutely numero uno to
investigate.

...
 		--> [driver] => K1 CHIP CLK H (fonz CPU clock)

Yeah; the Fonz also gets "MCLK L" on pin 19, though - not sure what that's
for. Eh, not important at the moment.

...
  The 4-bit counter looks to be generating some
additional phases 
Yeah, section 4.2 "Timimg" of the -11/24 TM talks about all the various
clocks in some detail.

...
  but it's also controlled by a bunch of other
signals. One of those
 signals is K6 BUF DCLO L which can hold the counter in reset, i.e.
 disable the Master/CPU clock (and LED). K6 BUF DCLO L is derived
 on-board from K2 P FAIL H 
Huh? BUF DCLO L is just BUS DCLO L, run through that DS8641 bus transceiver.

But yes, because DCLO can stop the clock, checking ACLO and DCLO is priority
numero uno in the debugging process, now. (Contrary to my previous fear, the
CPU might be OK, and it might just be a power supply issue.)

...
  which is derived from K2 BUS ACLO L 
I haven't bothered to check to see where BUF ACLO L (generated on K2) goes,
but I assume it's used in power-fail trapping stuff. (ISTR that PDP-11 PS's
sequence ACLO before DCLO, to allow power-fail trapping, before the machine is
frozen as DC power actually goes low.) Likewise, not important at the moment.

...
  which is input from BF1-in-funky-hex-box which I
presume is a bus
 connector pin. 
Yes; the ID ("BF2") is an indicator to that.

...
  Even if ACLO is good, there's a whack of logic on
the CPU board -
 including two monostables - just to get from ACLO to DCLO 
The import of those two monostables isn't completely clear to me. However,
notice that the output is fed through the DS8641 bus transceiver to _drive_
BUS DCLO; my _guess_ is that there's a delay between the PFAIL H input (which
comes from BUS ACLO L) and _the CPU_'s assertion of DCLO - i.e. if the P/S
goes bonkers and indicates ACLO, and doesn't promptly (after a suitable short
delay to allow for power-fail action) follow it with DCLO, as it is
_supposed_ to, the CPU will indicate DCLO on its own - and do it on the bus
so everbody else will freeze too.

Anyway, I think we've got as far as we can until ACLO and DCLO are checked.

I'm upgrading the CHWiki KDF11-U page to cover the stuff that's not in the
CPU chapter of the -11/24 TM, like the meaning of those on-board LED's, etc.

	Noel