9 Sep
2016
9 Sep
'16
7:11 p.m.
If your CPU is an 11/73 (which can directly
'access' [hate that verbism
:-] all of memory from ODT, unlike the 11/23 which is restricted to the
bottom 256KB), try playing around with a failing location, and its
alternative, directly, and see if a store of random data into one can be
read back directly from the other
Note: The 11/'73' CPU powers up with the cache enabled, even for ODT!
So if you write xxx into some location, if you then read it back, you will get
the correct data even if the memory location is busted - the CPU is getting
the (correct) data from the cache. To have your 'memory' reads and writes
actually go to the memory, you need to turn off the cache:
17777746/ 02000
Note that starting the machine does an INIT, which will again enable the
cache.
I'll start the Computer History wiki page for this
board with that info.
Started:
http://gunkies.org/w/index.php?title=CMV-4000
Currently has only the memory chip info, I'll add the config stuff as I get it
doped out.
Noel
9 Sep
9 Sep
9:17 p.m.
On Sep 9, 2016, at 6:11 PM, Noel Chiappa <jnc at mercury.lcs.mit.edu> wrote:
That?s a very good piece of information, I hadn?t considered that. I have 11/73.
I?ve checked the memory with ODT and can confirm the stuck bit.
I found that EK-MSV1Q-UG-002_MSV11Q_5-85.pdf describes how the CVMSAA diagnostic works.
"Section 1: Address Tests
These tests verify the uniqueness of every memory address.Test 1 writes and reads the
value of each memory word address into that memory location. After all memory has
been written, all locations are checked again. ?
I interpret this as mean it will deposit 1000 into @1000, and that will be read back as
1400
given the bad bit. So if you have stuck bit, the test for uniqueness gives a false
positive.
A comic ray probably took out a logic gate, as there is a pattern of stuck 1 bits in the
chip.
As soon as I pick up a spare chip, I start to get invasive. A careful clipped VCC is
easily
restored if its the wrong chip.
Jerry
If your CPU is an 11/73 (which can directly
'access' [hate that verbism
:-] all of memory from ODT, unlike the 11/23 which is restricted to the
bottom 256KB), try playing around with a failing location, and its
alternative, directly, and see if a store of random data into one can be
read back directly from the other
Note: The 11/'73' CPU powers up with the cache enabled, even for ODT!
So if you write xxx into some location, if you then read it back, you will get
the correct data even if the memory location is busted - the CPU is getting
the (correct) data from the cache. To have your 'memory' reads and writes
actually go to the memory, you need to turn off the cache:
17777746/ 02000
Note that starting the machine does an INIT, which will again enable the
cache.
25 Sep
25 Sep
9:34 p.m.
On Sep 9, 2016, at 8:17 PM, Jerry Weiss <jsw at ieee.org> wrote:
On Sep 9, 2016, at 6:11 PM, Noel Chiappa <jnc at mercury.lcs.mit.edu> wrote:
That?s a very good piece of information, I hadn?t considered that. I have 11/73.
I?ve checked the memory with ODT and can confirm the stuck bit.
Finally got back to this. First clipped VCC on the suspect
and confirmed that the bank and address range was the same as the original error.
So finally pulled out the soldering iron and replaced as chip. Back to memory test
and all is now good.
R VMJA??
VMJAB0.BIC
CVMJAB0 ECC/PARITY MEMORY DIAGNOSTIC
11/83 CACHE AVAILABLE
END PASS #QV 1
END PASS # 2
END PASS # 3
END PASS # 4
END PASS # 5
END PASS # 6
END PASS # 7
END PASS # 8
END PASS # 9
END PASS # 10
END PASS # 11
END PASS # 12
END PASS # 13
I board fixed, one to go. Thanks for the support.
Jerry
If your CPU is an 11/73 (which can directly
'access' [hate that verbism
:-] all of memory from ODT, unlike the 11/23 which is restricted to the
bottom 256KB), try playing around with a failing location, and its
alternative, directly, and see if a store of random data into one can be
read back directly from the other
Note: The 11/'73' CPU powers up with the cache enabled, even for ODT!
So if you write xxx into some location, if you then read it back, you will get
the correct data even if the memory location is busted - the CPU is getting
the (correct) data from the cache. To have your 'memory' reads and writes
actually go to the memory, you need to turn off the cache:
17777746/ 02000
Note that starting the machine does an INIT, which will again enable the
cache.
2856
days inactive
2873
days old
2 comments
2 participants
participants (2)
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jnc＠mercury.lcs.mit.edu -
jsw＠ieee.org